[coreboot-gerrit] Change in coreboot[master]: cpu/x86/mtrr/xip_cache.c: Fix inconsistent message

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36585 )

Change subject: cpu/x86/mtrr/xip_cache.c: Fix inconsistent message
......................................................................

cpu/x86/mtrr/xip_cache.c: Fix inconsistent message

Change-Id: Ic99e61632664f86cc12507f2ddffa364fdd79202
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36585
Reviewed-by: Nico Huber 
Reviewed-by: Arthur Heymans 
Tested-by: build bot (Jenkins) 
---
M src/cpu/x86/mtrr/xip_cache.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Arthur Heymans: Looks good to me, approved

diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c
index 112c0dfb..9968eea 100644
--- a/src/cpu/x86/mtrr/xip_cache.c
+++ b/src/cpu/x86/mtrr/xip_cache.c
@@ -63,7 +63,7 @@
    if (cpu_info.x86 == 0xf) {
    	printk(BIOS_NOTICE,
    	       "PROG_RUN: CPU does not support caching ROM\n"
-		       "The next stage will run slowly\n");
+		       "The next stage will run slowly!\n");
    	return;
    }