Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33379 )
Change subject: soc/intel: Provide SPD manufacturer ID and module type to SMBIOS ......................................................................
soc/intel: Provide SPD manufacturer ID and module type to SMBIOS
The DIMM manufacturing ID was not being initialized and so the DIMMs were not described in SMBIOS tables properly.
The module type can also be provided, but the SMBIOS code expects SPD module type values from DDR2 so the DDR3/4 values are adjusted before sending to SMBIOS.
BUG=b:134897498 BRANCH=sarien TEST=dump and compare with dmidecode
BEFORE: Type: DDR4 Manufacturer: Unknown (0) Form Factor: Unknown
AFTER: Type: DDR4 Manufacturer: Hynix/Hyundai Form Factor: SODIMM
Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42 Signed-off-by: Duncan Laurie dlaurie@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 7 files changed, 40 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index 16d14d9..1dc5cee 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -93,6 +93,8 @@ NULL, /* SPD not available */ memory_info_hob->DataWidth, 0, + 0, + src_dimm->MfgId, 0); index++; } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 59e1330..0fbab0b 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -99,7 +99,9 @@ src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth, 0, - 0); + 0, + src_dimm->MfgId, + src_dimm->SpdModuleType); index++; } } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index fa530a2..9dadb2d 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -116,7 +116,9 @@ src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth, memory_info_hob->VddVoltage[memProfNum], - memory_info_hob->EccSupport); + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); index++; } } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index e3ed3a2..d315e15 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -17,14 +17,38 @@ #include "smbios.h" #include <string.h> #include <console/console.h> +#include <device/dram/ddr3.h>
/* Fill the SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.*/ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support) + bool ecc_support, u16 mod_id, u8 mod_type) { + dimm->mod_id = mod_id; + /* Translate to DDR2 module type field that SMBIOS code expects. */ + switch (mod_type) { + case SPD_DIMM_TYPE_SO_DIMM: + dimm->mod_type = SPD_SODIMM; + break; + case SPD_DIMM_TYPE_72B_SO_CDIMM: + dimm->mod_type = SPD_72B_SO_CDIMM; + break; + case SPD_DIMM_TYPE_72B_SO_RDIMM: + dimm->mod_type = SPD_72B_SO_RDIMM; + break; + case SPD_DIMM_TYPE_UDIMM: + dimm->mod_type = SPD_UDIMM; + break; + case SPD_DIMM_TYPE_RDIMM: + dimm->mod_type = SPD_RDIMM; + break; + case SPD_DIMM_TYPE_UNDEFINED: + default: + dimm->mod_type = SPD_UNDEFINED; + break; + } dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; dimm->ddr_frequency = frequency; diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 12b8da0..97437ee 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -27,6 +27,6 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support); + bool ecc_support, u16 mod_id, u8 mod_type);
#endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index a09641c..b0eeb2e 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -101,7 +101,9 @@ src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth, memory_info_hob->VddVoltage[memProfNum], - memory_info_hob->EccSupport); + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); index++; } } diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 0eff793..83fc27e 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -129,7 +129,9 @@ src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, memory_info_hob->DataWidth, memory_info_hob->VddVoltage[memProfNum], - memory_info_hob->EccSupport); + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType); index++; } }