Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31951 )
Change subject: device/pciexp_device: Add set_L1_ss_latency() for pciexp device ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/31951/1/src/device/pciexp_device.c File src/device/pciexp_device.c:
https://review.coreboot.org/#/c/31951/1/src/device/pciexp_device.c@470 PS1, Line 470: PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 |
what i could see its more over intel specific hence its better to make a softlink and move actual i […]
The 'offset' parameter is found by searching a standard PCIE capability structure, so this function _would_ be placed here in global PCI scope, if it was more complex and did more than just alias pci_write_config32().
https://review.coreboot.org/#/c/31951/1/src/include/device/pciexp.h File src/include/device/pciexp.h:
https://review.coreboot.org/#/c/31951/1/src/include/device/pciexp.h@12 PS1, Line 12:
yes there is relation.
LTR snoop/non snoop field are like 16 bit registers
0-9: Latency value 10-12: Latency scale [000: Value times 1ns 001: Value times 32ns 010: Value times 1024ns 011 - Value time 32768ns 100 - value times 1048576ns 101 - Value times 33554432ns 110-111 reserved ]
Just rename the #define from _VALUE to _3146US for now. Someone with deeper PCIe knowledge should revisit this, why only couple SOCs program this.
Looks like it is (value << (5 * scale)) in nanoseconds And the reverse function is something like:
scale = log2(latency_ns) / 5 value = latency_ns >> (scale * 5)
https://review.coreboot.org/#/c/31951/1/src/soc/intel/common/block/pcie/pcie... File src/soc/intel/common/block/pcie/pcie.c:
https://review.coreboot.org/#/c/31951/1/src/soc/intel/common/block/pcie/pcie... PS1, Line 71: No need to change anything here, fine as-is.