Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72391 )
Change subject: mb/google/skyrim: Update ASPM settings for the NVMe device ......................................................................
mb/google/skyrim: Update ASPM settings for the NVMe device
This enables L1.2 for the SSD port.
link_hotplug is unused on Mendocino, so remove it while I'm here, just as code cleanup. This has no functional difference.
Enabling L1.2 on other devices currently causes problems. Debug is ongoing.
BUG=b:265890321 TEST=Build & boot, look at states enabled in lspci. Test device functionality.
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@amd.corp-partner.google.com Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com --- M src/mainboard/google/skyrim/port_descriptors.c 1 file changed, 27 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Matt DeVillier: Looks good to me, approved
diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index d745bd7..0046a33 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -16,7 +16,6 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, .clk_req = CLK_REQ2, }, { /* SD */ @@ -29,7 +28,6 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, .gpio_group_id = GPIO_27, .clk_req = CLK_REQ1, }, @@ -43,7 +41,7 @@ .link_speed_capability = GEN3, .turn_off_unused_lanes = true, .link_aspm = ASPM_L1, - .link_hotplug = 3, + .link_aspm_L1_2 = true, .gpio_group_id = GPIO_6, .clk_req = CLK_REQ0, },