Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40337 )
Change subject: soc/intel/{apl, cnl, skl}: Add sanity check of SA_PCIEX_LENGTH_MIB ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40337/1/src/soc/intel/skylake/syste... File src/soc/intel/skylake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/40337/1/src/soc/intel/skylake/syste... PS1, Line 17: #if (CONFIG_SA_PCIEX_LENGTH_MIB > 0x100) /* Max length is 256MB */ : #error "Invalid SA_PCIEX_LENGTH_MIB selection!" : #endif
The code from src/soc/intel is used not only for SoC. […]
Yes, looking at EDS, it appears that maximum PCIEXBAR length support for SKL/KBL is 256MB.
With CB:40235 we are adding new soc capability without any additional guard at common layer hence thinking guard at soc layer might ensure wrong selection by users.