Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39143 )
Change subject: mb/51nb/x210: update devicetree ......................................................................
mb/51nb/x210: update devicetree
- Add USB ports for SD card reader, fingerprint reader, and internal port. - Enable PcieRpClkReqSupport on NVMe root port, correct values for ClkReq/ClkSrc. - Remove hotplug support from PCIe root port used for WiFi
Derived from x210_test branch of HarryKipper's repo: https://github.com/harrykipper/coreboot
Change-Id: Ib64629ada4726e5edc080608f71a51f56a9b747c Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/51nb/x210/devicetree.cb 1 file changed, 6 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/39143/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index c67f3a3..c91ddd3 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -171,17 +171,19 @@ register "PcieRpClkSrcNumber[3]" = "1" register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "1" - register "PcieRpHotPlug[3]" = "1"
register "PcieRpEnable[8]" = "1" # NVMe controller - register "PcieRpClkReqSupport[8]" = "0" - register "PcieRpClkReqNumber[8]" = "2" - register "PcieRpClkSrcNumber[8]" = "2" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" + register "PcieRpClkSrcNumber[8]" = "4" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) + register "usb2_ports[2]" = "USB2_PORT_FLEX(OC1)" # FPR + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC1)" # SD + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC1)" # INT register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # webcam register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # WiFi PCIe port USB