[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197

[Srinidhi N Kaushik (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Dossym Nurmukhanov, Nick Vaccaro, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41974

to look at the new patch set (#2).

Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197
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vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197

Update FSP headers for Tiger Lake platform generated based FSP
version 3197, which includes below additional UPDs:

FSPM:
CmdMirror
RMTBIT
FSPS:
SataPortsEnableDitoConfig

BUG=b:157725468
BRANCH=none
TEST=build and boot volteer

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I23d6baacc3d963b473280c7fdb1e5df950cd7ca8
---
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
2 files changed, 41 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/41974/2