Attention is currently required from: Angel Pons, Evgeny Zinoviev. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42447 )
Change subject: nb/intel/sandybridge/gma.c: Fix lock bits setting ......................................................................
Patch Set 2: Code-Review+1
(2 comments)
Patchset:
PS2: I guess we just need better commit messages here. Looking at the bug tracker and this series, it seems this the only patch that affects SNB, so should be what actually fixed your X220?
Are the steps numbered in the reference code? If not, I'd like to keep the numbering of the BIOS Spec, with comments what changed, e.g. /* Bit 4 (lock) must be set later. */
File src/northbridge/intel/sandybridge/gma.c:
https://review.coreboot.org/c/coreboot/+/42447/comment/aa8e4f10_b4c08ffa PS1, Line 376: gtt_write(0xa004, 0x00000000);
Reference code writes zero at this point, and locks it later.
Please leave a comment or at least mention it in the commit message. The code currently does what Intel documented, if we deviate, we should mention why.