Attention is currently required from: Hung-Te Lin.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69183 )
Change subject: lib/coreboot_table: Rename lb_fill_pcie ......................................................................
lib/coreboot_table: Rename lb_fill_pcie
By convention 'fill_lb_xxx' is used.
Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/soc/mediatek/common/pcie.c M src/soc/qualcomm/common/pcie_common.c 4 files changed, 17 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/69183/1
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 4aab80e..e209e4b 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -22,7 +22,7 @@ enum cb_err fill_lb_serial(struct lb_serial *serial); void lb_add_console(uint16_t consoletype, void *data);
-enum cb_err lb_fill_pcie(struct lb_pcie *pcie); +enum cb_err fill_lb_pcie(struct lb_pcie *pcie);
/* Define this in mainboard.c to add board-specific table entries. */ void lb_board(struct lb_header *header); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6c09cb1..0f20735 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -33,7 +33,7 @@ void lb_string_platform_blob_version(struct lb_header *header); #endif
-__weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie) +__weak enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { return CB_ERR_NOT_IMPLEMENTED; } @@ -129,7 +129,7 @@ { struct lb_pcie pcie = { .tag = LB_TAG_PCIE, .size = sizeof(pcie) };
- if (lb_fill_pcie(&pcie) != CB_SUCCESS) + if (fill_lb_pcie(&pcie) != CB_SUCCESS) return;
memcpy(lb_new_record(header), &pcie, sizeof(pcie)); diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index febb76d..fd93665 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -211,7 +211,7 @@ pci_domain_set_resources(dev); }
-enum cb_err lb_fill_pcie(struct lb_pcie *pcie) +enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { if (!pci_root_bus()) return CB_ERR; diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index e27b0fc..2f53e28 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -414,7 +414,7 @@ * Fill coreboot table with PCIe info. * It allows exporting this info to payloads. */ -enum cb_err lb_fill_pcie(struct lb_pcie *pcie) +enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { pcie_cntlr_cfg_t *pcierc = qcom_pcie_cfg.cntlr_cfg; pcie->ctrl_base = (uintptr_t)pcierc->dbi_base;