[coreboot-gerrit] Change in ...coreboot[master]: soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30998 )

Change subject: soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout
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Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/#/c/30998/1/src/soc/amd/stoneyridge/include/soc/... 
File src/soc/amd/stoneyridge/include/soc/gpio.h:

https://review.coreboot.org/#/c/30998/1/src/soc/amd/stoneyridge/include/soc/... 
PS1, Line 465: #define GPIO_IN_DEBOUNCE_DISABLED	(0 | GPIO_TIMEBASE_61uS)
> "just 0" would (silently) imply GPIO_TIMEBASE_61uS, which is just one of 4 possible "zeros". […]

sgtm