[coreboot-gerrit] Change in coreboot[master]: riscv: add trampoline in MBR block to support boot mode 1

[Philipp Hug (Code Review)]

Hello Jonathan Neuschäfer, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/27397

to look at the new patch set (#6).

Change subject: riscv: add trampoline in MBR block to support boot mode 1
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riscv: add trampoline in MBR block to support boot mode 1

Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.

Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.

Further changes are needed in the bootblock
Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug 
---
M Documentation/mainboard/sifive/hifive-unleashed.md
M util/riscv/sifive-gpt.py
2 files changed, 12 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/27397/6