Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40612 )
Change subject: soc/intel/jasperlake: Enable end of post support in FSP ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40612/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40612/5//COMMIT_MSG@11 PS5, Line 11: applicable
Pls refer to EOP requirement documented in Doc#619830(section 3.6). […]
My understanding here is that FSP in API mode runs only PEI. There is no DXE. And so it is essential to set the EOP to happen in PEI. Aamir - does this match your understanding? If yes, can you please add this detail to commit message. Right now, it is not very clear "why" this change is being made.
https://review.coreboot.org/c/coreboot/+/40612/7/src/soc/intel/jasperlake/ch... File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/40612/7/src/soc/intel/jasperlake/ch... PS7, Line 151: /* : * ME End of Post configuration : * 0 - Disable EOP. : * 1 - Send in PEI (Applicable for coreboot) : * 2 - Send in DXE (Not applicable for coreboot) : */ : enum { : EOP_Disabled, : EOP_PEI, : EOP_DXE, : } EndOfPost; Any reason why this is living in chip.h instead of fsp_params.c? It doesn't seem to be configurable by mainboard anyways.