[coreboot-gerrit] Change in coreboot[master]: soc/mediatek: Fix USB enumeration issue

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

soc/mediatek: Fix USB enumeration issue

Some USB 3.0 devices fail to be enumerated after USB reset, and xhci
port status register shows the device is disconnected. After measuring
the USB signal, we found that the USB disconnect threshold was lower and
that the disconnect event was triggered unexpectedly.

USB designers suggest changing discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150
Tested-by: build bot (Jenkins) 
Reviewed-by: Hung-Te Lin 
---
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved

diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h
index 8a36c6a..22704e7 100644
--- a/src/soc/mediatek/common/include/soc/usb_common.h
+++ b/src/soc/mediatek/common/include/soc/usb_common.h
@@ -70,6 +70,8 @@
 #define PA6_RG_U2_ISO_EN			(0x1 << 31)
 #define PA6_RG_U2_BC11_SW_EN		(0x1 << 23)
 #define PA6_RG_U2_OTG_VBUSCMP_EN	(0x1 << 20)
+#define PA6_RG_U2_DISCTH		(0xf << 4)
+#define PA6_RG_U2_DISCTH_VAL(x)		((0xf & (x)) << 4)
 #define PA6_RG_U2_SQTH			(0xf << 0)
 #define PA6_RG_U2_SQTH_VAL(x)		((0xf & (x)) << 0)

diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c
index dcb9307..328bf66 100644
--- a/src/soc/mediatek/common/usb.c
+++ b/src/soc/mediatek/common/usb.c
@@ -76,6 +76,10 @@
    /* Set USB 2.0 slew rate value */
    clrsetbits_le32(&phy->u2phy.usbphyacr5,
    	PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
+
+	/* Set USB 2.0 disconnect threshold */
+	clrsetbits_le32(&phy->u2phy.usbphyacr6,
+		PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15));
 }

static void u3phy_power_on(void)