Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 )
Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/dedede... PS5, Line 95: 65
Thanks for this info.
How did we arrive to this 65 deg C value ? We need to discuss with ODM on this new value 65 deg C. Does it meet skin spec as per on-going discussion on b:169691800 ?
https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/dedede... PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden : register "options.tsr[0].desc" = ""Memory"" : register "options.tsr[1].desc" = ""Ambient"" : register "options.tsr[2].desc" = ""Charger"" : register "options.tsr[3].desc" = ""5V regulator""
They are two separate devices so it's kind of tricky to share registers between them
Tim, I did not get your comment, please elaborate. Here, in this patch the only new code change is TSR1 temperature trip value changed from 51 to 65 deg C. All other entries here are the same as previous existing ones, including sensor description entries. So, I feel we might not need to add the same sensor description entries again here because these are common entries for the system which won't change. Thanks.