Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41674 )
Change subject: soc/intel/common/block/sata: Fix SATA detection issue between Ports 3-7 ......................................................................
Patch Set 4:
@Nico, what should be our direction here, fix this register programming issue or remove those finalize code from here. I'm with first one.
I would just remove the whole driver. Looking at its history: * It was added in a broken state. The issue it reportedly fixed can only mean that FSP left the AHCI Ports Implemented register in an inconsistent state (or maybe just unitialized, but this driver didn't initialize it either). * It was most likely added to help with a broken FSP1.1. Which we don't use anymore. * It was initially written for SKL and KBL U/Y. Still other, incompatible PCI IDs were added which resulted in wild patching. And it still writes a different register for all other platforms than originally intended. * It needed a lot of maintenance, probably sucked thousands of dollars out of the coreboot community and still continues to. But it most likely doesn't provide any value since FSP2.0. * Doing things in FSP and coreboot redundantly can increase complexity and costs by a power of 2.