Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40467 )
Change subject: soc/intel/cannonlake: Report driver strength by _DSM in eMMC ACPI device ......................................................................
Patch Set 8:
(2 comments)
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40467/7/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/scs.asl:
https://review.coreboot.org/c/coreboot/+/40467/7/src/soc/intel/cannonlake/ac... PS7, Line 100: Return(Buffer() {0x0, 0x02})
Does the kernel care about HS200/HS400 mode as well?
hi Tim, i checked the speed before. it's still hs400 and HS_TIMING: 0x43 (bit[7:4] is 40ohm)
clock: 200000000 Hz actual clock: 200000000 Hz vdd: 7 (1.65 - 1.95 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 10 (mmc HS400 enhanced strobe) signal voltage: 1 (1.80 V) driver type: 0 (driver type B)
https://review.coreboot.org/c/coreboot/+/40467/7/src/soc/intel/cannonlake/ac... PS7, Line 105: eMMC
Actual driver strength or preferred driver strength?
Done