Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41903
to look at the new patch set (#14).
Change subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: FSP ww24 release and soc change ......................................................................
vendorcode/intel/fsp/fsp2_0/cpx_sp: FSP ww24 release and soc change
Intel CPX-SP FSP ww22 release fixed issues related to FSP_NV_STORAGE HOB. The end of end flow of using memory training data to generate FSP_NV_STORAGE HOB and using memory training data passed from bootloader to skip memory training, works now.
This release also added UPD parameters to support IIO bifuration.
Intel CPX-SP ww24 release has following updates: a. Removed a number of unnecessary UPD parameters, suh as mmiolSize, mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate. b. Added UPD parameters to support PCIe ports configuration. c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit, in additin to PCIe resource memory base/limit.
With ww24 release, the issue with PCIe link training persists. On YV3 config A, the onboard NIC card has x4 connection to port 2D. This NIC device is not recognized by FSP.
Corresponding soc/intel/xeon_sp/cpx change is made: * There are changes in PLATFORM_DATA structure, so hob_display.c is updated. * There are changes in UPD parameters, so romstage.c is updated.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa --- M src/soc/intel/xeon_sp/cpx/hob_display.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 5 files changed, 200 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/41903/14