[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Add SoC ACPI directory for Panther Lake

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim.

Subrata Banik has posted comments on this change by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )

Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................

Patch Set 81:

(3 comments)

File src/soc/intel/pantherlake/acpi/pcie.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/0b227b66_2f7e47d7?usp... :
PS81, Line 269: Device (RP11)
              : {
              : 	Name (_ADR, 0x00060002)
              : 
              : 	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
              : 	Field (RPCS, AnyAcc, NoLock, Preserve)
              : 	{
              : 		, 24,
              : 		RPPN, 8,	/* Root Port Number */
              : 	}
              : 
              : 	Method (_PRT)
              : 	{
              : 		Return (IRQM (RPPN))
              : 	}
              : }
              : 
              : Device (RP12)
              : {
              : 	Name (_ADR, 0x00060003)
              : 
              : 	OperationRegion (RPCS, PCI_Config, 0x4c, 4)
              : 	Field (RPCS, AnyAcc, NoLock, Preserve)
              : 	{
              : 		, 24,
              : 		RPPN, 8,	/* Root Port Number */
              : 	}
              : 
              : 	Method (_PRT)
              : 	{
              : 		Return (IRQM (RPPN))
              : 	}
don't you need SoC Kconfig guard for PTL-H that has 10 PCIe RPs?

File src/soc/intel/pantherlake/acpi/southbridge.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/c6ce4bc0_2478a6d2?usp... :
PS81, Line 11: #if CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB)
can we have a PTL SoC that can decide to drop PCD P2SB support if not then I would default select ioe_pcr.asl.

File src/soc/intel/pantherlake/acpi/tcss_xhci.asl:

https://review.coreboot.org/c/coreboot/+/83772/comment/8473b0bf_78ba9d01?usp... :
PS81, Line 37: // D3COLD_SUPPORT
use `/* ... */`