HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31409
Change subject: sb/intel/common: Use big enough type for left-shift ......................................................................
sb/intel/common: Use big enough type for left-shift
Change-Id: I662b66513db48ff1742255beef524762cdaf4dc8 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/spi.c 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31409/1
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 7f07a72..7a1070c 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -33,7 +33,7 @@ #define D31F0_ETR3 0xac #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) -#define ETR3_CF9LOCK (1 << 31) +#define ETR3_CF9LOCK (1UL << 31) #define D31F0_GPIO_ROUT 0xb8 #define GPI_DISABLE 0x00 #define GPI_IS_SMI 0x01 diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 60c0b8d..4e8e80f 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -984,7 +984,7 @@ #define ICH7_SPI_FPR_LIMIT_SHIFT 12 #define ICH9_SPI_FPR_LIMIT_SHIFT 16 #define ICH9_SPI_FPR_RPE (1 << 15) /* Read Protect */ -#define SPI_FPR_WPE (1 << 31) /* Write Protect */ +#define SPI_FPR_WPE (1UL << 31) /* Write Protect */
static u32 spi_fpr(u32 base, u32 limit) {