Marco Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35881 )
Change subject: mb/google/octopus/variants/fleex: Update GPIOs to fix EMR ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... File src/mainboard/google/octopus/variants/fleex/gpio.c:
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 29: PAD_NC(GPIO_138, UP_20K),
The PEN_PDCT_ODL is leveraged GPIO_138.
I can understand it is physically connected to GPIO_138 but what I mean is there is not FW or kernel driver or SW used this pin?
https://review.coreboot.org/c/coreboot/+/35881/1/src/mainboard/google/octopu... PS1, Line 32: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),
There is an external inverter on the PEN_RESET_ODL. […]
I know there is an external inverter on the PEN_RESET_ODL and this is why overridetree.cb shows [1] (ACTIVE_HIGH). And the power sequence currently should be looked like (from acpi_device_add_power_res())
power on DUT -> GPIO_140 LOW (chip not in reset state) -> (boot to kernel) -> GPIO_140 HIGH (chip in reset state) -> (no enable gpio) -> GPIO_140 LOW (chip leave in reset state) -> (no stop gpio)
Then you can see in case of cold boot, 1. chip should be kept in reset state in coreboot stage but it is not 2. in kernel side, the GPIO_140 High to low is without delay so I doubt it's pulse width might be not enough?
[1] "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"