[coreboot-gerrit] [S] Change in coreboot[main]: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration

[Anastasios Koutian (Code Review)]

Anastasios Koutian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83271?usp=email )

Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
......................................................................

cpu/intel/model_206ax: Allow turbo boost ratio limit configuration

Tested on ThinkPad T420 with the i7-3940XM.

Change-Id: I1c65a129478e8ac2c4f66eb3c6aa2507358f82ad
Signed-off-by: Anastasios Koutian 
---
M src/cpu/intel/model_206ax/chip.h
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_206ax/model_206ax_init.c
3 files changed, 40 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/83271/1

diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h
index aa4c0ef..40d0fd3 100644
--- a/src/cpu/intel/model_206ax/chip.h
+++ b/src/cpu/intel/model_206ax/chip.h
@@ -56,6 +56,11 @@
    /* PSI states only have an effect when in Package C3 or higher */
    struct psi_state pp0_psi[3];	/* Power states for Primary Plane (Icc) */
    struct psi_state pp1_psi[3];	/* Power states for Secondary Plane (IAXG) */
+
+	int turbo_ratio_limit_1c; /* Turbo Ratio Limit for 1 core active */
+	int turbo_ratio_limit_2c; /* Turbo Ratio Limit for 2 cores active */
+	int turbo_ratio_limit_3c; /* Turbo Ratio Limit for 3 cores active */
+	int turbo_ratio_limit_4c; /* Turbo Ratio Limit for 4 cores acrive */
 };

#endif /* __CPU_INTEL_MODEL_206AX_CHIP_H__ */
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 2338f29..defc935 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -46,6 +46,7 @@
 #define MSR_LT_LOCK_MEMORY		0x2e7
 #define MSR_PLATFORM_INFO		0xce
 #define  PLATFORM_INFO_SET_TDP		(1 << 29)
+#define  PLATFORM_INFO_SET_TURBO_RATIO_LIMIT		(1 << 28)

#define MSR_MISC_PWR_MGMT		0x1aa
 #define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index dd71d0f..3207304 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -175,6 +175,33 @@
    }
 }

+static void configure_turbo_ratio_limits(struct cpu_intel_model_206ax_config *conf)
+{
+		msr_t msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+
+		if(conf->turbo_ratio_limit_1c) {
+			msr.lo &= ~0xff;
+			msr.lo |= (conf->turbo_ratio_limit_1c);
+		}
+
+		if(conf->turbo_ratio_limit_2c) {
+			msr.lo &= ~(0xff << 8);
+			msr.lo |= (conf->turbo_ratio_limit_2c << 8);
+		}
+
+		if(conf->turbo_ratio_limit_3c) {
+			msr.lo &= ~(0xff << 16);
+			msr.lo |= (conf->turbo_ratio_limit_3c << 16);
+		}
+
+		if(conf->turbo_ratio_limit_4c) {
+			msr.lo &= ~(0xff << 24);
+			msr.lo |= (conf->turbo_ratio_limit_4c << 24);
+		}
+
+		wrmsr(MSR_TURBO_RATIO_LIMIT, msr);
+}
+
 static void configure_c_states(struct device *dev)
 {
    struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info;
@@ -298,6 +325,13 @@
    	msr.lo |= PP1_CURRENT_LIMIT_LOCK;
    	wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
    }
+
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if(msr.lo & PLATFORM_INFO_SET_TURBO_RATIO_LIMIT) {
+			configure_turbo_ratio_limits(conf);
+	} else {
+			printk(BIOS_NOTICE, "%s: Programmable ratio limit for turbo mode is disabled\n", dev_path(dev));
+	}
 }

static void configure_thermal_target(struct device *dev)