Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17674
-gerrit
commit abb3d694d86b8d977a713e5752686c10cd34c1bf Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Jun 25 11:40:00 2016 +0300
intel/gm45: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/lenovo/t400/romstage.c | 17 ++++------------- src/mainboard/lenovo/x200/romstage.c | 17 ++++------------- src/mainboard/roda/rk9/romstage.c | 17 ++++------------- src/northbridge/intel/gm45/northbridge.c | 17 ----------------- src/southbridge/intel/i82801ix/i82801ix.h | 4 ---- src/southbridge/intel/i82801ix/smi.c | 13 ++----------- 6 files changed, 14 insertions(+), 71 deletions(-)
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 821b87f..d110d4f 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <lib.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> @@ -156,18 +157,8 @@ void mainboard_romstage_entry(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
cbmem_initted = !cbmem_recovery(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume && cbmem_initted) { - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); - } -#endif + + romstage_handoff_init(cbmem_initted && s3resume); + printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 8c97ae1..49c5528 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <lib.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> @@ -157,18 +158,8 @@ void mainboard_romstage_entry(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
cbmem_initted = !cbmem_recovery(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume && cbmem_initted) { - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); - } -#endif + + romstage_handoff_init(cbmem_initted && s3resume); + printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index e9a6a81..720f628 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <lib.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> @@ -187,18 +188,8 @@ void mainboard_romstage_entry(unsigned long bist) init_iommu();
cbmem_initted = !cbmem_recovery(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume && cbmem_initted) { - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); - } -#endif + + romstage_handoff_init(cbmem_initted && s3resume); + printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index aaa6749..af62f12 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -216,28 +216,11 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, };
- static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; - } -#endif } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index afe4aa7..af4efcd 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -218,10 +218,6 @@ #define FD_SAD1 (1 << 2) /* SATA #1 */
-#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #ifndef __ACPI__ #ifndef __ASSEMBLER__
diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index dd0915a..34fbad4 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -314,16 +315,6 @@ static void smm_relocate(void)
static int smm_handler_copied = 0;
-static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -337,7 +328,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */
- if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);