build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39599 )
Change subject: nb/intel/sandybridge: Tidy up code and comments ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39599/3/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/northbridge.c:
https://review.coreboot.org/c/coreboot/+/39599/3/src/northbridge/intel/sandy... PS3, Line 41: uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID) & 0xf0; line over 96 characters
https://review.coreboot.org/c/coreboot/+/39599/3/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/39599/3/src/northbridge/intel/sandy... PS3, Line 2818: for (timC = 0; timC < MAX_TIMC; timC++) { Too many leading tabs - consider code refactoring