[coreboot-gerrit] Change in coreboot[master]: soc/intel/icelake: Add alignment check for TSEG base and size

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36542 )

Change subject: soc/intel/icelake: Add alignment check for TSEG base and size
......................................................................

soc/intel/icelake: Add alignment check for TSEG base and size

This patch ensures to not set SMRR if TSEG base is not align with TSEG size

Change-Id: I77d1cb2fd287f45859cde37a564ea7c147d5633f
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36542
Reviewed-by: Arthur Heymans 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/icelake/smmrelocate.c
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index edcc49d..8f56ad6 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -178,6 +178,13 @@
    const u32 rmask = ~(4 * KiB - 1);

smm_region(&tseg_base, &tseg_size);
+
+	if (!IS_ALIGNED(tseg_base, tseg_size)) {
+		printk(BIOS_WARNING,
+		     "TSEG base not aligned with TSEG SIZE! Not setting SMRR\n");
+		return;
+	}
+
    smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */