Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36165 )
Change subject: drivers/intel/fsp2_0: Move Debug options to "Debugging" ......................................................................
drivers/intel/fsp2_0: Move Debug options to "Debugging"
TODO: Is verify HOBS really 'Debugging' and should this really be optional?
Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/Kconfig M src/drivers/intel/fsp2_0/Kconfig 2 files changed, 40 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/36165/1
diff --git a/src/Kconfig b/src/Kconfig index 4c71f28..80efb12 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,46 @@ mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file.
+config DISPLAY_FSP_CALLS_AND_STATUS + bool "Display the FSP calls and status" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP call entry point and parameters prior to calling FSP + and display the status upon return from FSP. + +config DISPLAY_FSP_HEADER + bool "Display the FSP header" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP header information when the FSP file is found. + +config DISPLAY_HOBS + bool "Display the hand-off-blocks" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the FSP HOBs which are provided for coreboot. + +config DISPLAY_UPD_DATA + bool "Display UPD data" + depends on PLATFORM_USES_FSP2_0 + default n + help + Display the user specified product data prior to memory + initialization. + +config VERIFY_HOBS + bool "Verify the FSP hand-off-blocks" + depends on PLATFORM_USES_FSP2_0 + default n + help + Verify that the HOBs required by coreboot are returned by FSP and + that the resource HOBs are in the correct order and position. + + + endmenu
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 1e84dab..fee5de4 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -39,32 +39,6 @@ Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added.
-config DISPLAY_FSP_CALLS_AND_STATUS - bool "Display the FSP calls and status" - default n - help - Display the FSP call entry point and parameters prior to calling FSP - and display the status upon return from FSP. - -config DISPLAY_FSP_HEADER - bool "Display the FSP header" - default n - help - Display the FSP header information when the FSP file is found. - -config DISPLAY_HOBS - bool "Display the hand-off-blocks" - default n - help - Display the FSP HOBs which are provided for coreboot. - -config DISPLAY_UPD_DATA - bool "Display UPD data" - default n - help - Display the user specified product data prior to memory - initialization. - config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" depends on FSP_CAR @@ -161,13 +135,6 @@ stack with coreboot/bootloader. Sync this value with Platform FSP integration guide recommendation.
-config VERIFY_HOBS - bool "Verify the FSP hand-off-blocks" - default n - help - Verify that the HOBs required by coreboot are returned by FSP and - that the resource HOBs are in the correct order and position. - config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n