build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39317 )
Change subject: soc/intel/tigerlake: Enable CNVi Mode ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39317/1/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39317/1/src/soc/intel/tigerlake/chi... PS1, Line 214: trailing whitespace