[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Disable XHCI LFPS power management

[Marx Wang (Code Review)]

Hello build bot (Jenkins), Paul Menzel, Angel Pons, Kane Chen, Andrey Petrov, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40255

to look at the new patch set (#21).

Change subject: soc/intel/apollolake: Disable XHCI LFPS power management
......................................................................

soc/intel/apollolake: Disable XHCI LFPS power management

Provide the option to disable XHCI LFPS power management.
If the option is set in the devicetree, the bits[7:4] in
XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated
from default 9 to 0.

BUG=b:146768983
BRANCH=None
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
     the image to the device. Run following command to check if
     bits[7:4] is set 0:
     >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"

Signed-off-by: Marx Wang 
Change-Id: Ic603e3b919d8b443c6ede8bb5e46e2de07fcb856
---
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/chip.h
2 files changed, 39 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/40255/21