Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35373 )
Change subject: drivers/elog: Add elog_boot_notify() ......................................................................
drivers/elog: Add elog_boot_notify()
Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/include/elog.h M src/northbridge/intel/nehalem/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c 10 files changed, 16 insertions(+), 25 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index d86d3ab..67bea32 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -48,8 +48,7 @@
s3wake = params->power_state->prev_sleep_state == ACPI_S3;
- if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) - boot_count_increment(); + elog_boot_notify(s3wake);
/* Perform remaining SOC initialization */ soc_pre_ram_init(params); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 5765fb7..a075f01 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -392,8 +392,7 @@ struct memranges memmap; struct range_entry freeranges[2];
- if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) - boot_count_increment(); + elog_boot_notify(s3wake);
if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); diff --git a/src/include/elog.h b/src/include/elog.h index 9bb05ad..0574819 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -274,6 +274,12 @@ #endif u32 boot_count_increment(void);
+static inline void elog_boot_notify(int s3_resume) +{ + if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) + boot_count_increment(); +} + /* * Callback from GSMI handler to allow platform to log any wake source * information. diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 1f413e3..5bdb5d5 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -139,8 +139,7 @@ s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3);
- if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) - boot_count_increment(); + elog_boot_notify(s3_resume);
/* Device Enable */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 1b402dc..55f2928 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -74,8 +74,7 @@
s3resume = southbridge_detect_s3_resume();
- if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) - boot_count_increment(); + elog_boot_notify(s3resume);
post_code(0x38);
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 9882d91..257ae67 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -49,12 +49,10 @@ console_init();
mainboard_romstage_entry_s3(s3_resume); + elog_boot_notify(s3_resume);
if (!s3_resume) { post_code(0x40); - - if (CONFIG(ELOG_BOOT_COUNT)) - boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 4032d3f..2228c1a 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -97,6 +97,7 @@ load_smu_fw1();
mainboard_romstage_entry_s3(s3_resume); + elog_boot_notify(s3_resume);
bsp_agesa_call();
@@ -132,8 +133,6 @@ msr_t sys_cfg = rdmsr(SYSCFG_MSR); sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; wrmsr(SYSCFG_MSR, sys_cfg); - if (CONFIG(ELOG_BOOT_COUNT)) - boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7348d2b..7c129e2 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -185,10 +185,7 @@
printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
-#if CONFIG(ELOG_BOOT_COUNT) - if (prev_sleep_state != ACPI_S3) - boot_count_increment(); -#endif + elog_boot_notify(prev_sleep_state == ACPI_S3);
/* Initialize RAM */ raminit(&mp, prev_sleep_state); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index ebb72cb..96218f4 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -62,6 +62,8 @@ /* Get power state */ rp.power_state = fill_power_state();
+ elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3); + /* Print useful platform information */ report_platform_info();
@@ -80,10 +82,6 @@
rp.pei_data.boot_mode = rp.power_state->prev_sleep_state;
- if (CONFIG(ELOG_BOOT_COUNT) - && rp.power_state->prev_sleep_state != ACPI_S3) - boot_count_increment(); - /* Print ME state before MRC */ intel_me_status();
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index c362577..25ffdc4 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -124,10 +124,7 @@
wake_from_s3 = southbridge_detect_s3_resume();
-#if CONFIG(ELOG_BOOT_COUNT) - if (!wake_from_s3) - boot_count_increment(); -#endif + elog_boot_notify(wake_from_s3);
/* Report if we are waking from s3. */ return wake_from_s3;