Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35160 )
Change subject: soc/intel/{apl,cnl,dnv,icl,skl} : Fix random hang introduced by CB:34893 ......................................................................
soc/intel/{apl,cnl,dnv,icl,skl} : Fix random hang introduced by CB:34893
This patch fixes random hang seeing during ramstage after including below MTRR range with CB:34893
MTRR Range: Start=0 End=1000000 (Size 1000000)
TEST=Able to build and boot CML-hatch and ICLRVP.
With this CL
MTRR Range: Start=99000000 End=9a000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000)
<Booted to OS>
Without this CL
MTRR Range: Start=99000000 End=9a000000 (Size 1000000) MTRR Range: Start=0 End=1000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000)
<Hang in ramstage>
Change-Id: I7553a5f4ab4cff4a2158c9b6e0f7058f5c028f99 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/apollolake/memmap.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/icelake/memmap.c M src/soc/intel/skylake/memmap.c 5 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/35160/1
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index bda43bb..88236587 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -76,4 +76,8 @@ */ smm_region(&smm_base, &smm_size); postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + + pcf->skip_common_mtrr = 1; + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index f0c21d9..5192a88 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -280,4 +280,9 @@ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + pcf->skip_common_mtrr = 1; + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); + } diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index f7b2e07..bb1504d 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -102,4 +102,8 @@ */ smm_region(&smm_base, &smm_size); postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + + pcf->skip_common_mtrr = 1; + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 71368c6..d179ea1 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -278,4 +278,8 @@ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); top_of_ram -= 16*MiB; postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + + pcf->skip_common_mtrr = 1; + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 4c3c58a..7d1662d 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -319,5 +319,9 @@ */ smm_region(&smm_base, &smm_size); postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + + pcf->skip_common_mtrr = 1; + /* Cache the memory-mapped boot media. */ + postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } #endif