[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Enable TCSS USB ports

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54331 )

Change subject: mb/intel/adlrvp: Enable TCSS USB ports
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mb/intel/adlrvp: Enable TCSS USB ports

This patch enables TCSS USB ports.

BUG=b:184324979
TEST=Verified on ADL-P RVP

Signed-off-by: Sridhar Siricilla 
Change-Id: I92bf30a56f3befad3f806bff5d29d39b6754b079
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/54331/1

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 23913cc..c94c8c3 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -15,6 +15,9 @@
    # Enable HECI1 interface
    register "HeciEnabled" = "1"

+	# TCSS USB port enable
+	register "UsbTcPortEn" = "0x7"
+
    # FSP configuration

# Enable CNVi BT