Hello Haridhar Kalvala,
I'd like you to do a code review. Please visit
https://review.coreboot.org/26940
to review the following change.
Change subject: soc/intel/skylake: Enable low power S0Idle capability ......................................................................
soc/intel/skylake: Enable low power S0Idle capability
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0 if S0ix is enabled for the platform. This also sets the FSPUPD to indicate the status of S0ix on the platform.
BUG=b:79559085 TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table - FADT.Flags[21] bit.
Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210 Signed-off-by: Haridhar Kalvala haridhar.kalvala@intel.com Signed-off-by: Rajneesh Bhardwaj rajneesh.bhardwaj@intel.com --- M src/soc/intel/skylake/acpi.c 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/26940/1
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index be1200b..560b20c 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -234,6 +234,8 @@
void acpi_fill_fadt(acpi_fadt_t *fadt) { + const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = dev->chip_info; const uint16_t pmbase = ACPI_BASE_ADDRESS;
/* Use ACPI 3.0 revision */ @@ -282,6 +284,9 @@ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+ if(config->s0ix_enable) + fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; + fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; fadt->reset_reg.bit_offset = 0;