Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39034 )
Change subject: soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switch ......................................................................
soc/mediatek/mt8183: Correct EMI bandwidth threshold for DVFS switch
Because eMCP and discrete DDR devices have different DVFS tables, their EMI bandwidth thresholds should also be different. When the EMI total bandwidth reaches the threshold, the system will notify DVFS module to perform DVFS switch for system performance in low power states.
This patch increases the threshold from 0xa to 0xd for eMCP DDR devices so that DVFS switch will be less likely to happen.
The register table of EMI_BWCT0 is incorrect in the datasheet. According to the hardware design, BW_2ND_INT_BW_THR should be in bits [30:24] instead of [22:16]. However, the logic in DRAM driver is correct, aligned with the hardware design, so we don't need to correct it.
BRANCH=kukui BUG=b:142358843 TEST=bootup pass
Change-Id: I82c3c70bcd90df3fdd613c0353aba0f176bc82bc Signed-off-by: Huayang Duan huayang.duan@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39034 Reviewed-by: Hung-Te Lin hungte@chromium.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 4 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 07d1cc8..e7cbda1 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -299,8 +299,10 @@
setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4); setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4); - - write32(&emi_regs->bwct0, 0x0a000705); + if (CONFIG(MT8183_DRAM_EMCP)) + write32(&emi_regs->bwct0, 0x0d000705); + else + write32(&emi_regs->bwct0, 0x0a000705); write32(&emi_regs->bwct0_3rd, 0x0);
/* EMI QoS 0.5 */