Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40952 )
Change subject: nb/intel/sandybridge: Correct IOSAV register notes ......................................................................
nb/intel/sandybridge: Correct IOSAV register notes
The IOSAV register descriptions are plagued with errors and nonsense. Using `git blame` to find the culprit... Zoinks! Turns out it was me!
Rewrite the comment so that the difference between a sub-sequence and a command is clear. Also, expand the descriptions that could be ambiguous and fix some insane blunders. CKE and ODT fields are per DIMM and rank!
Change-Id: Ie384304c565f962fe58baa231c15109eb3d284aa Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/mchbar_regs.h 1 file changed, 46 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/40952/1
diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h index 5f46e70..38d7d00 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/mchbar_regs.h @@ -5,40 +5,47 @@ #define __SANDYBRIDGE_MCHBAR_REGS_H__
/* - * ### IOSAV command queue notes ### + * ### IOSAV memory controller interface poking state machine notes ### * - * Intel provides a command queue of depth four. - * Every command is configured by using multiple MCHBAR registers. - * On executing the command queue, you have to specify its depth (number of commands). + * IOSAV brings batch processing to memory training algorithms. The hardware is capable of + * executing a sequence of DRAM commands, which can be composed of up to four subsequences. + * A subsequence (from now on, subseq) consists of executing the same DRAM command for a + * configurable number of times, with adjustable delay between the commands, as well as the + * address auto-incrementing rate (every how many commands) and size (amount to increment). + * Every subseq can be programmed into several MCHBAR registers, which are evenly spaced. + * When firing up IOSAV, one is required to specify the number of subseqs it should use. * * The macros for these registers can take some integer parameters, within these bounds: * channel: [0..1] * index: [0..3] * lane: [0..8] * - * Note that these ranges are 'closed': both endpoints are included. + * Note that any ranges like these are 'closed': both endpoints are included. * * * - * ### Register description ### + * ### Register descriptions ### * * IOSAV_n_SP_CMD_ADDR_ch(channel, index) - * Sub-sequence command addresses. Controls the address, bank address and slotrank signals. + * Defines the address, bank and rank settings. When a subseq begins to execute, the + * address fields define the address of the first command in the subseq. The address + * updates after each command as per the rules defined in the "IOSAV_n_ADDR_UPDATE" + * registers, and the updated address is then loaded back into this register. * * Bitfields: - * [0..15] Row / Column Address. + * [0..15] Row / Column Address. Define the ADDR pins when issuing a DRAM command. * [16..18] The result of (10 + [16..18]) is the number of valid row bits. * Note: Value 1 is not implemented. Not that it really matters, though. * Value 7 is reserved, as the hardware does not support it. - * [20..22] Bank Address. + * [20..22] Bank select, encoded. * [24..25] Rank select. Let's call it "ranksel", as it is mentioned later. * * IOSAV_n_ADDR_UPDATE_ch(channel, index) - * How the address shall be updated after executing the sub-sequence command. + * How the address shall be updated after the execution of a command in the subseq. * * Bitfields: - * [0] Increment CAS/RAS by 1. - * [1] Increment CAS/RAS by 8. + * [0] Increment RAS/CAS address by 1. + * [1] Increment RAS/CAS address by 8. * [2] Increment bank select by 1. * [3..4] Increment rank select by 1, 2 or 3. * [5..9] Known as "addr_wrap". Address bits will wrap around the [addr_wrap..0] range. @@ -53,21 +60,25 @@ * 1: Update every second command run. That is, half of the command rate. * N: Update after N command runs without updates. * - * [16..17] LFSR behavior on the deselect cycles (when no sub-seq command is issued): + * [16..17] LFSR behavior on the deselect cycles (when no subseq command is issued): * 0: No change w.r.t. the last issued command. * 1: LFSR XORs with address & command (excluding CS), but does not update. * 2: LFSR XORs with address & command (excluding CS), and updates. * * IOSAV_n_SP_CMD_CTRL_ch(channel, index) - * Special command control register. Controls the DRAM command signals. + * Defines how the DRAM command lines shall be driven in each command of the subseq. * * Bitfields: - * [0] !RAS signal. - * [1] !CAS signal. - * [2] !WE signal. - * [4..7] CKE, per rank and channel. - * [8..11] ODT, per rank and channel. - * [12..15] Chip select, per rank and channel. It works as follows: + * [0] !RAS signal (as driven electrically). + * [1] !CAS signal (as driven electrically). + * [2] !WE signal (as driven electrically). + * + * [4] CKE, for DIMM 0 Rank 0. + * [5] CKE, for DIMM 0 Rank 1. + * [6] CKE, for DIMM 1 Rank 0. + * [7] CKE, for DIMM 1 Rank 1. + * [8..11] ODT, per DIMM & Rank (same encoding as CKE). + * [12..15] Chip select, per DIMM and Rank. It works as follows: * * entity CS_BLOCK is * port ( @@ -91,27 +102,29 @@ * [17] Auto Precharge. Only valid when using 10 row bits! * * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) - * Sub-sequence parameters. Controls repetititons, delays and data orientation. + * The parameters of the subseq: number of repetitions of the command, the delay between + * command executions, wait cycles after completing this subseq and before the next one, + * and the data direction of the command (read, write, neither, or both read and write). * * Bitfields: - * [0..8] Number of repetitions of the sub-sequence command. - * [10..14] Gap, number of clock-cycles to wait before sending the next command. - * [16..24] Number of clock-cycles to idle between sub-sequence commands. - * [26..27] The direction of the data. - * 00: None, does not handle data + * [0..8] Number of repetitions of the DRAM command of this subseq. + * [10..14] Number of DCLK cycles to wait between two successive DRAM commands. + * [16..24] Number of DCLK cycles to idle after this subseq and before the next subseq. + * [26..27] The direction of the data: + * 00: None (non-data command) * 01: Read * 10: Write * 11: Read & Write * * IOSAV_n_ADDRESS_LFSR_ch(channel, index) - * 23-bit LFSR state register. It is written into the LFSR when the sub-sequence is loaded, - * and then read back from the LFSR when the sub-sequence is done. + * 23-bit LFSR state register. It is written into the LFSR when the subseq is loaded, and + * then read back from the LFSR when the subseq is done. * * Bitfields: * [0..22] LFSR state. * * IOSAV_SEQ_CTL_ch(channel) - * Control the sequence level in IOSAV: number of sub-sequences, iterations, maintenance... + * IOSAV sequence settings: number of subseqs, iterations, stop on error, maintenance... * * Bitfields: * [0..7] Number of full sequence executions. When this field becomes non-zero, then the @@ -125,7 +138,7 @@ * and ZQXS operations can take place. * * [17] Stop-on-error mode: Whether to stop sequence execution when an error occurs. - * [18..19] Number of sub-sequences. The programmed value is the index of the last sub-seq. + * [18..19] Number of subseqs. The programmed value is the index of the last valid subseq. * [20] If set, keep refresh disabled until the next sequence execution. * DANGER: Refresh must be re-enabled within the (9 * tREFI) period! * @@ -133,8 +146,9 @@ * bit [20] is also set, or was set on the previous sequence. This bit exists so * that the sequence machine can be used as a timer without affecting the memory. * - * [23] If set, a output pin is asserted on the first detected error. This output can - * be used as a trigger for an oscilloscope or a logic analyzer, which is handy. + * [23] If set, an output pin is asserted on the first detected error. This output can + * be used as a trigger for an oscilloscope or a logic analyzer, which is pretty + * useful for debugging (if you have the equipment and know where this pin is). * * IOSAV_DATA_CTL_ch(channel) * Data-related controls in IOSAV mode. @@ -156,7 +170,6 @@ * [4] PANIC: The refresh machine issued a Panic Refresh, and IOSAV was aborted. * [5] RCOMP: RComp failure. Unused, consider Reserved. * [6] Cleared with a new sequence, and set when done and refresh counter is drained. - * */
/* Indexed register helper macros */