[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40789 )

Change subject: soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register
......................................................................

soc/amd/stoneyridge: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f
Signed-off-by: Elyes HAOUAS 
---
M src/soc/amd/stoneyridge/psp.c
1 file changed, 4 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/40789/1

diff --git a/src/soc/amd/stoneyridge/psp.c b/src/soc/amd/stoneyridge/psp.c
index 88bd61d..5a4cd4d 100644
--- a/src/soc/amd/stoneyridge/psp.c
+++ b/src/soc/amd/stoneyridge/psp.c
@@ -12,7 +12,8 @@

void soc_enable_psp_early(void)
 {
-	u32 base, limit, cmd;
+	u32 base, limit;
+	u16 cmd;

/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
    base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
@@ -25,9 +26,9 @@
    pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);

/* Enable memory access and master */
-	cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
+	cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND);
    cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
-	pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
+	pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd);
 };

void *soc_get_mbox_address(void)