Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42516 )
Change subject: src: s/__FUNCTION__/__func__/ ......................................................................
src: s/__FUNCTION__/__func__/
The former is not standard C, and we primarily use the latter form.
Change-Id: Ia7091b494ff72588fb6910710fd72165693c1ac5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/commonlib/include/commonlib/stdlib.h M src/drivers/pc80/tpm/tis.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c M src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c M src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c M src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c M src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c M src/vendorcode/cavium/bdk/libdram/dram-internal.h M src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c M src/vendorcode/cavium/bdk/libdram/libdram.c 12 files changed, 53 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/42516/1
diff --git a/src/commonlib/include/commonlib/stdlib.h b/src/commonlib/include/commonlib/stdlib.h index 307406f..374fe16 100644 --- a/src/commonlib/include/commonlib/stdlib.h +++ b/src/commonlib/include/commonlib/stdlib.h @@ -29,7 +29,7 @@ } return ret; } -#define xmalloc(size) xmalloc_work((size), __FILE__, __FUNCTION__, __LINE__) +#define xmalloc(size) xmalloc_work((size), __FILE__, __func__, __LINE__)
static inline void *xzalloc_work(size_t size, const char *file, const char *func, int line) @@ -38,7 +38,7 @@ memset(ret, 0, size); return ret; } -#define xzalloc(size) xzalloc_work((size), __FILE__, __FUNCTION__, __LINE__) +#define xzalloc(size) xzalloc_work((size), __FILE__, __func__, __LINE__)
void *dma_malloc(size_t size); int dma_coherent(void *ptr); diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 185df34..e18f9af 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -395,7 +395,7 @@
didvid = tpm_read_did_vid(0); if (!didvid || (didvid == 0xffffffff)) { - printf("%s: No TPM device found\n", __FUNCTION__); + printf("%s: No TPM device found\n", __func__); return TPM_DRIVER_ERR; }
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index e65b8e5..1f267f9 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -416,7 +416,7 @@ u32 eop_ack;
/* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + printk(BIOS_NOTICE, "ME: %s\n", __func__); if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { printk(BIOS_ERR, "ME: END OF POST message failed\n"); return -1; @@ -513,7 +513,7 @@ /* Check if the MBP is ready */ if (!gmes.mbp_rdy) { printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __FUNCTION__); + __func__); path = ME_ERROR_BIOS_PATH; }
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index aeab0c7..cdae271 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -529,7 +529,7 @@ };
/* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + printk(BIOS_NOTICE, "ME: %s\n", __func__); if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) { /* No response means reset will happen shortly... */ halt(); @@ -551,7 +551,7 @@ u32 eop_ack;
/* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__); + printk(BIOS_NOTICE, "ME: %s\n", __func__); if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) { printk(BIOS_ERR, "ME: END OF POST message failed\n"); return -1; @@ -698,7 +698,7 @@ /* Check if the MBP is ready */ if (!hfs2.mbp_rdy) { printk(BIOS_CRIT, "%s: mbp is not ready!\n", - __FUNCTION__); + __func__); path = ME_ERROR_BIOS_PATH; }
diff --git a/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c b/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c index fc9ac35..9b17745 100644 --- a/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c +++ b/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c @@ -70,7 +70,7 @@ case BDK_CSR_TYPE_RVU_PFVF_BAR2: case BDK_CSR_TYPE_RVU_VF_BAR2: /* Handled by inline code, we should never get here */ - bdk_error("%s: Passed type that should be handled inline\n", __FUNCTION__); + bdk_error("%s: Passed type that should be handled inline\n", __func__); break;
case BDK_CSR_TYPE_PCCBR: @@ -80,7 +80,7 @@ case BDK_CSR_TYPE_MDSB: case BDK_CSR_TYPE_PCICONFIGEP_SHADOW: case BDK_CSR_TYPE_PCICONFIGEPVF: - bdk_error("%s: Register not supported\n", __FUNCTION__); + bdk_error("%s: Register not supported\n", __func__); break;
case BDK_CSR_TYPE_SYSREG: @@ -99,7 +99,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC0_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 1: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -109,7 +109,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC1_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 2: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -119,7 +119,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC2_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 3: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -127,7 +127,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN83XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC3_CN83XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 4: dev_con.u = BDK_PCC_DEV_CON_E_PCIERC4; @@ -136,7 +136,7 @@ dev_con.u = BDK_PCC_DEV_CON_E_PCIERC5; break; default: - bdk_error("%s: Illegal PCIe bus number\n", __FUNCTION__); + bdk_error("%s: Illegal PCIe bus number\n", __func__); return -1; } return bdk_pcie_config_read32(node, 100 + dev_con.cn8.ecam, dev_con.s.bus, dev_con.s.func >> 3, dev_con.s.func & 7, address); @@ -180,7 +180,7 @@ case BDK_CSR_TYPE_RVU_PFVF_BAR2: case BDK_CSR_TYPE_RVU_VF_BAR2: /* Handled by inline code, we should never get here */ - bdk_error("%s: Passed type that should be handled inline\n", __FUNCTION__); + bdk_error("%s: Passed type that should be handled inline\n", __func__); break;
case BDK_CSR_TYPE_PCCBR: @@ -190,7 +190,7 @@ case BDK_CSR_TYPE_MDSB: case BDK_CSR_TYPE_PCICONFIGEP_SHADOW: case BDK_CSR_TYPE_PCICONFIGEPVF: - bdk_error("%s: Register not supported\n", __FUNCTION__); + bdk_error("%s: Register not supported\n", __func__); break;
case BDK_CSR_TYPE_SYSREG: @@ -210,7 +210,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC0_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 1: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -220,7 +220,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC1_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 2: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -230,7 +230,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC2_CN81XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 3: if (CAVIUM_IS_MODEL(CAVIUM_CN88XX)) @@ -238,7 +238,7 @@ else if (CAVIUM_IS_MODEL(CAVIUM_CN83XX)) dev_con.u = BDK_PCC_DEV_CON_E_PCIERC3_CN83XX; else - bdk_fatal("Update PCICONFIG in %s\n", __FUNCTION__); + bdk_fatal("Update PCICONFIG in %s\n", __func__); break; case 4: dev_con.u = BDK_PCC_DEV_CON_E_PCIERC4; @@ -247,7 +247,7 @@ dev_con.u = BDK_PCC_DEV_CON_E_PCIERC5; break; default: - bdk_error("%s: Illegal PCIe bus number\n", __FUNCTION__); + bdk_error("%s: Illegal PCIe bus number\n", __func__); return; } bdk_pcie_config_write32(node, 100 + dev_con.cn8.ecam, dev_con.s.bus, dev_con.s.func >> 3, dev_con.s.func & 7, address, value); diff --git a/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c b/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c index 0f75da2..81e1a78 100644 --- a/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c +++ b/src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c @@ -162,7 +162,7 @@ } } else - bdk_error("N%d.QLM%d: Unsupported chip, update %s()\n", node, qlm, __FUNCTION__); + bdk_error("N%d.QLM%d: Unsupported chip, update %s()\n", node, qlm, __func__); }
/** diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c index 0efe697..6c92a59 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c @@ -49,7 +49,7 @@ { int phy_status = 0;
- BDK_TRACE(PHY, "%s In SGMII mode for Marvell PHY 88E1512\n", __FUNCTION__); + BDK_TRACE(PHY, "%s In SGMII mode for Marvell PHY 88E1512\n", __func__); /* Switch to Page 18 */ phy_status = bdk_mdio_write(node, mdio_bus, mdio_addr, 22, 18); if (phy_status < 0) @@ -89,7 +89,7 @@
int bdk_if_phy_marvell_setup(bdk_node_t node, int qlm, int mdio_bus, int phy_addr) { - BDK_TRACE(PHY,"In %s\n",__FUNCTION__); + BDK_TRACE(PHY,"In %s\n",__func__);
/* Check if the PHY is marvell PHY we expect */ int phy_status = bdk_mdio_read(node, mdio_bus, phy_addr, BDK_MDIO_PHY_REG_ID1); @@ -100,13 +100,13 @@ /* Switch the marvell PHY to the correct mode */ bdk_qlm_modes_t qlm_mode = bdk_qlm_get_mode(node, qlm);
- BDK_TRACE(PHY,"%s: QLM:%d QLM_MODE:%d\n",__FUNCTION__, qlm, qlm_mode); + BDK_TRACE(PHY,"%s: QLM:%d QLM_MODE:%d\n",__func__, qlm, qlm_mode);
if ((qlm_mode != BDK_QLM_MODE_SGMII_1X1) && (qlm_mode != BDK_QLM_MODE_SGMII_2X1)) return 0;
- BDK_TRACE(PHY,"%s: Detected Marvell Phy in SGMII mode\n", __FUNCTION__); + BDK_TRACE(PHY,"%s: Detected Marvell Phy in SGMII mode\n", __func__); for (int port = 0; port < 2; port++) { setup_marvell_phy(node, mdio_bus, phy_addr + port); diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c index 26c4fd4..796d699 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c @@ -91,7 +91,7 @@ uint16_t reg_val; uint16_t mask;
- BDK_TRACE(PHY,"In %s\n",__FUNCTION__); + BDK_TRACE(PHY,"In %s\n",__func__); BDK_TRACE(PHY,"Loading init script for VSC8514\n");
ptr = init_script_rev_a; diff --git a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c index 303b276..5582e08 100644 --- a/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c +++ b/src/vendorcode/cavium/bdk/libbdk-hal/qlm/bdk-qlm-cn81xx.c @@ -773,7 +773,7 @@ } else { - bdk_error("Update %s for qlm auto config of this chip\n",__FUNCTION__); + bdk_error("Update %s for qlm auto config of this chip\n",__func__); return; } BDK_CSR_MODIFY(c, node, BDK_GSERX_REFCLK_SEL(qlm), diff --git a/src/vendorcode/cavium/bdk/libdram/dram-internal.h b/src/vendorcode/cavium/bdk/libdram/dram-internal.h index 02bf0d0..a54d2a4 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-internal.h +++ b/src/vendorcode/cavium/bdk/libdram/dram-internal.h @@ -158,7 +158,7 @@ #define DEVICE_TYPE DDR4_SPD_KEY_BYTE_DEVICE_TYPE // same for DDR3 and DDR4 spd_ddr_type = read_spd(node, dimm_config, DEVICE_TYPE);
- debug_print("%s:%d spd_ddr_type=0x%02x\n", __FUNCTION__, __LINE__, spd_ddr_type); + debug_print("%s:%d spd_ddr_type=0x%02x\n", __func__, __LINE__, spd_ddr_type);
/* we return only DDR4 or DDR3 */ return (spd_ddr_type == 0x0C) ? DDR4_DRAM : DDR3_DRAM; diff --git a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c index 291fe85..ebbe836 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c @@ -199,7 +199,7 @@ }
debug_print("N%d.LMC%d: %s: returning bin %d for MTS %d\n", - node, lmc, __FUNCTION__, ret, mts_speed); + node, lmc, __func__, ret, mts_speed);
return ret; } @@ -857,9 +857,9 @@ // run the test one last time // print whether there are errors or not, but only when verbose... bdk_watchdog_poke(); - debug_print("N%d: %s: Start running test one last time\n", node, __FUNCTION__); + debug_print("N%d: %s: Start running test one last time\n", node, __func__); tot_errors = run_dram_tuning_threads(node, num_lmcs, bytemask); - debug_print("N%d: %s: Finished running test one last time\n", node, __FUNCTION__); + debug_print("N%d: %s: Finished running test one last time\n", node, __func__); if (tot_errors) ddr_print2("%s Timing Final Test: errors 0x%x\n", mode_str, tot_errors);
@@ -893,7 +893,7 @@ orig_coremask = bdk_get_running_coremask(node); /* FIXME(dhendrix): %lx --> %llx */ ddr_print4("N%d: %s: Starting cores (mask was 0x%llx)\n", - node, __FUNCTION__, orig_coremask); + node, __func__, orig_coremask); /* FIXME(dhendrix): don't call bdk_init_cores(). */ // bdk_init_cores(node, ~0ULL & ~orig_coremask); dram_tune_max_cores = bdk_get_num_running_cores(node); @@ -979,7 +979,7 @@ ddr_interface_64b = !lmc_config.s.mode32b;
// do setup for each active LMC - debug_print("N%d: %s: starting LMCs setup.\n", node, __FUNCTION__); + debug_print("N%d: %s: starting LMCs setup.\n", node, __func__); for (lmc = 0; lmc < num_lmcs; lmc++) {
#if 0 @@ -1019,7 +1019,7 @@ #endif
// perform cleanup on all active LMCs - debug_print("N%d: %s: starting LMCs cleanup.\n", node, __FUNCTION__); + debug_print("N%d: %s: starting LMCs cleanup.\n", node, __func__); for (lmc = 0; lmc < num_lmcs; lmc++) {
/* Restore ECC for DRAM tests */ @@ -1066,12 +1066,12 @@ uint64_t reset_coremask = 0; if (reset_coremask) { /* FIXME(dhendrix): %lx --> %llx */ - ddr_print4("N%d: %s: Stopping cores 0x%llx\n", node, __FUNCTION__, + ddr_print4("N%d: %s: Stopping cores 0x%llx\n", node, __func__, reset_coremask); bdk_reset_cores(node, reset_coremask); } else { /* FIXME(dhendrix): %lx --> %llx */ - ddr_print4("N%d: %s: leaving cores set to 0x%llx\n", node, __FUNCTION__, + ddr_print4("N%d: %s: leaving cores set to 0x%llx\n", node, __func__, orig_coremask); }
@@ -1215,7 +1215,7 @@ setup_lfsr_pattern(node, lmc, 0); errors = test_dram_byte_hw(node, lmc, phys_addr, mode, xor_data); VB_PRT(VBL_DEV2, "%s: LFSR at A:0x%012llx errors 0x%x\n", - __FUNCTION__, phys_addr, errors); + __func__, phys_addr, errors); } else { for (pattern = 0; pattern < NUM_BYTE_PATTERNS; pattern++) { pattern_p = byte_patterns[pattern]; @@ -1224,7 +1224,7 @@ errs = test_dram_byte_hw(node, lmc, phys_addr, mode, xor_data);
VB_PRT(VBL_DEV2, "%s: PATTERN %d at A:0x%012llx errors 0x%x\n", - __FUNCTION__, pattern, phys_addr, errs); + __func__, pattern, phys_addr, errs);
errors |= errs; } /* for (pattern = 0; pattern < NUM_BYTE_PATTERNS; pattern++) */ @@ -1270,7 +1270,7 @@ hw_rank_offset = 1ull << (28 + lmcx_config.s.pbank_lsb - lmcx_config.s.rank_ena + (num_lmcs/2));
debug_print("N%d: %s: starting LMC%d with rank offset 0x%lx\n", - node, __FUNCTION__, lmc, hw_rank_offset); + node, __func__, lmc, hw_rank_offset);
// start of pattern loop // we do the set of tests for each pattern supplied... diff --git a/src/vendorcode/cavium/bdk/libdram/libdram.c b/src/vendorcode/cavium/bdk/libdram/libdram.c index 740de84..e2c6017 100644 --- a/src/vendorcode/cavium/bdk/libdram/libdram.c +++ b/src/vendorcode/cavium/bdk/libdram/libdram.c @@ -437,21 +437,21 @@ // so, enable any non-running cores on this node, and leave them // running at the end... ddr_print("N%d: %s: Starting cores (mask was 0x%llx)\n", - node, __FUNCTION__, bdk_get_running_coremask(node)); + node, __func__, bdk_get_running_coremask(node)); bdk_init_cores(node, ~0ULL);
// must test for L2C locked here, cannot go on with it unlocked // FIXME: but we only need to worry about Node 0??? if (node == 0) { if (!l2c_is_locked) { // is unlocked, must lock it now - ddr_print("N%d: %s: L2C was unlocked - locking it now\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was unlocked - locking it now\n", node, __func__); // FIXME: this should be common-ized; it currently matches bdk_init()... bdk_l2c_lock_mem_region(node, 0, bdk_l2c_get_cache_size_bytes(node) * 3 / 4); } else { - ddr_print("N%d: %s: L2C was already locked - continuing\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was already locked - continuing\n", node, __func__); } } else { - ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__); + ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __func__); }
// call the tuning routines, no filtering... @@ -464,10 +464,10 @@ // FIXME: this should be common-ized; it currently matches bdk_init()... bdk_l2c_unlock_mem_region(node, 0, bdk_l2c_get_cache_size_bytes(node) * 3 / 4); } else { - ddr_print("N%d: %s: L2C was already locked - leaving it locked\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was already locked - leaving it locked\n", node, __func__); } } else { - ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__); + ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __func__); }
// make sure to clear memory and any ECC errs when done... @@ -605,21 +605,21 @@ // so, enable any non-running cores on this node, and leave them // running at the end... ddr_print("N%d: %s: Starting cores (mask was 0x%llx)\n", - node, __FUNCTION__, bdk_get_running_coremask(node)); + node, __func__, bdk_get_running_coremask(node)); bdk_init_cores(node, ~0ULL);
// must test for L2C locked here, cannot go on with it unlocked // FIXME: but we only need to worry about Node 0??? if (node == 0) { if (!l2c_is_locked) { // is unlocked, must lock it now - ddr_print("N%d: %s: L2C was unlocked - locking it now\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was unlocked - locking it now\n", node, __func__); // FIXME: this should be common-ized; it currently matches bdk_init()... bdk_l2c_lock_mem_region(node, 0, bdk_l2c_get_cache_size_bytes(node) * 3 / 4); } else { - ddr_print("N%d: %s: L2C was already locked - continuing\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was already locked - continuing\n", node, __func__); } } else { - ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__); + ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __func__); }
debug_print("N%d: Starting DRAM Margin ALL\n", node); @@ -659,10 +659,10 @@ // FIXME: this should be common-ized; it currently matches bdk_init()... bdk_l2c_unlock_mem_region(node, 0, bdk_l2c_get_cache_size_bytes(node) * 3 / 4); } else { - ddr_print("N%d: %s: L2C was already locked - leaving it locked\n", node, __FUNCTION__); + ddr_print("N%d: %s: L2C was already locked - leaving it locked\n", node, __func__); } } else { - ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__); + ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __func__); }
return 0;