Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38495 )
Change subject: [WIP] vc/amd/agesa/[...]/Proc/Mem: Fix uninitialized scalar variable ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38495/2/src/vendorcode/amd/agesa/f1... File src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c:
https://review.coreboot.org/c/coreboot/+/38495/2/src/vendorcode/amd/agesa/f1... PS2, Line 508: (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane]))
In no particular order, 0x10 is subtracted per 5b of 2.9.5.9.3 in Fam 15h BKDG: […]
Any news? Please also see a "DDR3 XMP support" change CB:40291 , since you're also digging that Proc/Mem AGESA code and maybe could share some ideas?