1 comment:
File src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mtthrcSeedTrain.c:
Patch Set #2, Line 508: (RxEnMemClkTested[ByteLane][MemClkCycle] ? RxEnMemClkSt[ByteLane][MemClkCycle] == TRUE : (TechPtr->ByteLaneError[ByteLane] && DlyWrittenToReg[ByteLane]))
In no particular order, 0x10 is subtracted per 5b of 2.9.5.9.3 in Fam 15h BKDG: […]
Any news? Please also see a "DDR3 XMP support" change CB:40291 , since you're also digging that Proc/Mem AGESA code and maybe could share some ideas?
To view, visit change 38495. To unsubscribe, or for help writing mail filters, visit settings.