Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46246 )
Change subject: mb/asrock/h110m/romstage.c: Correct FSP-M UPDs ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46246/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46246/1//COMMIT_MSG@13 PS1, Line 13: can be found using Intel Document #573387 Can they?
The only S target values I can find are for CFL-S 2DPC. If you want this to be accurate, you could say something like "can be guessed from".
With only that document as reference, there is still a chance that the first target value should be 60. For the better documented H values, it started with 50 for 1DPC and 60 for 2DPC, but that's for SO-DIMM. The 60 was later lowered to 50 (CFL-H), but not for regular DIMMs. So there is a slight chance that regular DIMMs always should have a 60 there. When they lowered it for the SO-DIMMs, a comment says that the old value wouldn't hurt.
I have no final suggestion here. A hunch tells me to take the 60 and comment that 50 is also possible.
One could also ask Intel, ofc.