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https://review.coreboot.org/c/coreboot/+/60731
to look at the new patch set (#15).
Change subject: soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config ......................................................................
soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` config
Since Tiger Lake platform, the HECI1 device can be disabled on Alder Lake platform using two different mechanism: A. Using PMC IPC command 0xA9. B. Sending SBI message under SMM.
In current scope of Alder Lake the default implementation is using (B) sending sbi message under SMM. A follow up patch to add the possible options and let platform to choose the applicable one.
List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Default enable HECI1 device in `chipset.cb`.
Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/smihandler.c 10 files changed, 2 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60731/15