Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Van Patten, Fred Reitberger, Felix Held.
Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71909 )
Change subject: soc/amd/mendocino: Separate STAPM and STT for DPTC ......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71909/comment/f9630e97_faffa237 PS10, Line 9: Separate the STAPM and STT for the DPTC parameter. To avoid unnecessary : parameters being applied to DPTC when STT is enabled, especially SPL.
What does this mean in practice? What boards have STT (STAPM) enabled, but not the other?
The STAPM is the default performance/thermal management for the AMD CPUs. Before STT enable, the CPU is rely on this feature to manager the performance. The legacy generation CPU (like FT4 stoney) still use STPAM only,and STT have been introduced on Ryzen serials.
Why do we want to support this, since it appears to essentially double the maintenance burden?
When the STT enabled, the SPL shouldn't be touch or change, it used for STAPM but not in STT, and it will confuse the STT calculation.
Can we state all boards must support/enable STT instead?
The STT is the POR for MDN platform, but before STT enabled, the CPU still use STAPM.