[coreboot-gerrit] [XS] Change in coreboot[main]: nb/intel/gm45/raminit: Use read32p()

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77971?usp=email )

Change subject: nb/intel/gm45/raminit: Use read32p()
......................................................................

nb/intel/gm45/raminit: Use read32p()

Built roda/rk9 with BUILD_TIMELESS=1 and the resulting coreboot.rom
remains identical.

Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092
Signed-off-by: Elyes Haouas 
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77971
Reviewed-by: Felix Singer 
Reviewed-by: Felix Held 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/gm45/raminit.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Felix Singer: Looks good to me, approved
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index a998d77..b7e0139 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1965,7 +1965,7 @@
    	jedec_command(rankaddr, DCC_CMD_ABP, 0);
    	jedec_command(rankaddr, DCC_CMD_CBR, 0);
    	udelay(1);
-		read32((void *)(rankaddr));
+		read32p(rankaddr);

jedec_command(rankaddr, DCC_SET_MREG, WR | CAS | BTinterleaved | BL8);
    	jedec_command(rankaddr, DCC_SET_EREGx(1), OCDdefault | ODT_150OHMS);