[coreboot-gerrit] Change in coreboot[master]: [TEST]soc/intel/tigerlake: unlock RTC memory

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39710 )

Change subject: [TEST]soc/intel/tigerlake: unlock RTC memory
......................................................................

[TEST]soc/intel/tigerlake: unlock RTC memory

Unlock RTC memory for OS to update info

Signed-off-by: Wonkyu Kim 
Change-Id: I63cec8a718285f424914e426d0399ed821588dfd
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/39710/1

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index a8be407..31968d9 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -107,6 +107,10 @@
    for (i = 0; i < 8; i++)
    	params->IomTypeCPortPadCfg[i] = 0x09000000;

+	/* TODO: before UPD is avaialbe for RtcMemoryLock (offset:0x0621) */
+	/*  params->RtcMemoryLock = 0 */
+	params->Reserved25[2] = 0;
+
    /* USB */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
    	params->PortUsb20Enable[i] = config->usb2_ports[i].enable;