[coreboot-gerrit] [M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS

[Patrick Rudolph (Code Review)]

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Maximilian Brune, Tim Chu.

Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email )

Change subject: cpu/x86/64bit: Install extended page tables in BSS
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Patch Set 6:

(1 comment)

Patchset:

PS6:
> Considering that we use 1GB pages for almost all platforms (especially the more recent ones) we don' […]

It's not about DRAM, but about MMIO. There's nothing in coreboot caring about/using DRAM above 4GiB. But MMIO can be anywhere in the address space, usually way beyond the possible usable/maximum DRAM space.

It would be possible to introduce `CPU_PT_ROM_MAP_GB_RAMSTAGE`, use it only for ramstage and let the SoC set an arbitrary limit that satisfies the needs in ramstage. It would generate big page-table in RO memory as it's currently done by `CPU_PT_ROM_MAP_GB`. There's a huge downside to this approach:

You cannot use BSS. BSS is free and doesn't need space in the SPI flash, nor in the CBFS stage cache. RO-memory needs space in the SPI flash and the CBFS stage cache.

Thus using big (2.1 MiB) page-tables in RO-memory does:
- Increase the size on SPI flash (depending on compression just a bit)
- Increase the stage loading times
- Increase the size used in the CBFS stage cache

With the current approach the SPI flash size and CBFS stage cache size remains the same.