[coreboot-gerrit] [S] Change in coreboot[main]: tgl mainboards: Move SATA related settings into SATA device scope

[Felix Singer (Code Review)]

Attention is currently required from: Nick Vaccaro.

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83249?usp=email )

Change subject: tgl mainboards: Move SATA related settings into SATA device scope
......................................................................

tgl mainboards: Move SATA related settings into SATA device scope

Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9
Signed-off-by: Felix Singer 
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
2 files changed, 11 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/83249/1

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 61d84cc..fd51840 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -122,12 +122,6 @@
    register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
    register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"

-	# Enable SATA
-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable[1]" = "1"
-	register "SataPortsDevSlp[1]" = "1"
-	register "SataPortsEnableDitoConfig[1]" = "1"
-
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoPci,
    	[PchSerialIoIndexI2C1]  = PchSerialIoPci,
@@ -460,7 +454,12 @@
    	device ref i2c2 on end
    	device ref i2c3 on end
    	device ref heci1 on end
-		device ref sata on end
+		device ref sata on
+			register "SataSalpSupport" = "1"
+			register "SataPortsEnable[1]" = "1"
+			register "SataPortsDevSlp[1]" = "1"
+			register "SataPortsEnableDitoConfig[1]" = "1"
+		end
    	device ref pcie_rp7 on end
    	device ref pcie_rp8 on
    		probe DB_SD SD_GL9755S
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index d820c7b..a42d16f 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -39,10 +39,6 @@
    register "PcieClkSrcUsage[2]" = "0x3"
    register "PcieClkSrcUsage[3]" = "0x8"

-	register "SataSalpSupport" = "1"
-	register "SataPortsEnable[0]" = "1"
-	register "SataPortsEnable[1]" = "1"
-
    # enabling EDP in PortA
    register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"

@@ -264,7 +260,11 @@
    	device ref csme2 off end
    	device ref heci3 off end
    	device ref heci4 off end
-		device ref sata on  end
+		device ref sata on
+			register "SataSalpSupport" = "1"
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
+		end
    	device ref i2c4 off end
    	device ref i2c5 on  end
    	device ref uart2 on  end