Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19016 )
Change subject: [Not For Merge] nb/intel/i945: Remove unused #define REFRESH_* ......................................................................
Patch Set 1:
(1 comment)
Oh indeed not tRFC but tREF or tRR like its called in ddr2.c
https://review.coreboot.org/#/c/19016/1/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c:
PS1, Line 848: if (refresh == 2) { : sysinfo->refresh = 1;
The code expects either 13 or 14 row address bits. With the usual 64ms The code expects either 13 or 14 row address bits. With the usual 64ms maximum refresh interval. This gives us either
64ms / 2^13 = 7.8us 64ms / 2^14 = 3.9us
Not sure if 14 row address bits is usual in DDR2.
Sure there is no off by one here? 15.625 μs is quite common/default (13 rows?)