29 Jan
2019
29 Jan
'19
4 a.m.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28648 )
Change subject: nb/intel/i945: Set CxDRT1 tRPALL bit if populated with 8-bank ......................................................................
Patch Set 9:
Why are both CxDRT1 registers programmed with the same value ? Wouldn't that break if one channel has 8banks DIMMs, but the other 16banks DIMMs? What does the datasheet say? Does both channels need to be kept in sync ?
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