Ronald G. Minnich (rminnich@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8038
-gerrit
commit c5581989203639ea40872b30f2c3a52321a688a4 Author: Ronald G. Minnich rminnich@gmail.com Date: Fri Jan 2 08:34:29 2015 -0800
Fix up our types
We chose the types u* and s* to match the Linux kernel a long time ago. Those names are short and to the point. The uint*_t and int*_t are names only a committee could have invented, given their basic ugliness. I would prefer to stick with the nice names, and here's one proposal to fix it.
I will be pretty surprised if this gets by jenkins.
Change-Id: I0273c56d296b9ef9fea317e90b07a82734ab48ec Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- src/arch/arm/armv7/cache.c | 8 +- src/arch/arm/armv7/exception.c | 38 ++-- src/arch/arm/armv7/mmu.c | 10 +- src/arch/arm/tables.c | 2 +- src/arch/arm64/armv8/cache.c | 12 +- src/arch/arm64/armv8/exception.c | 38 ++-- src/arch/arm64/tables.c | 4 +- src/arch/arm64/timestamp.c | 4 +- src/arch/riscv/rom_media.c | 2 +- src/arch/x86/boot/acpigen.c | 8 +- src/arch/x86/boot/cbmem.c | 8 +- src/arch/x86/boot/pirq_routing.c | 10 +- src/arch/x86/lib/cpu.c | 4 +- src/arch/x86/lib/exception.c | 6 +- src/arch/x86/lib/memset.c | 2 +- src/arch/x86/lib/pci_ops_conf1.c | 12 +- src/arch/x86/lib/pci_ops_mmconf.c | 12 +- src/arch/x86/lib/rom_media.c | 8 +- src/arch/x86/lib/thread.c | 16 +- src/console/post.c | 4 +- src/cpu/allwinner/a10/bootblock.c | 2 +- src/cpu/allwinner/a10/twi.c | 4 +- src/cpu/amd/agesa/family15rl/udelay.c | 8 +- src/cpu/amd/agesa/family15tn/udelay.c | 8 +- src/cpu/amd/dualcore/amd_sibling.c | 2 +- src/cpu/amd/dualcore/dualcore.c | 6 +- src/cpu/amd/model_fxx/model_fxx_init.c | 12 +- src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 2 +- src/cpu/amd/model_fxx/powernow_acpi.c | 28 +-- src/cpu/amd/mtrr/amd_mtrr.c | 20 +- src/cpu/intel/fsp_model_406dx/bootblock.c | 2 +- src/cpu/intel/haswell/monotonic_timer.c | 8 +- src/cpu/intel/speedstep/acpi.c | 4 +- src/cpu/intel/speedstep/speedstep.c | 4 +- src/cpu/ti/am335x/bootblock.c | 2 +- src/cpu/ti/am335x/dmtimer.c | 2 +- src/cpu/ti/am335x/header.c | 2 +- src/cpu/ti/am335x/monotonic_timer.c | 8 +- src/cpu/ti/am335x/uart.c | 6 +- src/cpu/x86/lapic/apic_timer.c | 8 +- src/cpu/x86/mp_init.c | 44 ++-- src/cpu/x86/mtrr/mtrr.c | 32 +-- src/cpu/x86/pae/pgtbl.c | 12 +- src/cpu/x86/smm/smm_module_loader.c | 6 +- src/cpu/x86/tsc/delay_tsc.c | 8 +- src/device/device.c | 4 +- src/device/oprom/yabel/device.c | 2 +- src/device/pci_device.c | 16 +- src/drivers/ams/as3722rtc.c | 8 +- src/drivers/emulation/qemu/cirrus.c | 8 +- src/drivers/i2c/tpm/tis.c | 16 +- src/drivers/i2c/tpm/tpm.c | 44 ++-- src/drivers/i2c/w83793/w83793.c | 4 +- src/drivers/intel/gma/intel_ddi.c | 4 +- src/drivers/intel/gma/intel_dp.c | 122 +++++------ src/drivers/maxim/max77686/max77686.c | 2 +- src/drivers/pc80/spkmodem.c | 4 +- src/drivers/pc80/tpm.c | 4 +- src/drivers/sil/3114/sil_sata.c | 2 +- src/drivers/spi/adesto.c | 10 +- src/drivers/spi/amic.c | 10 +- src/drivers/spi/atmel.c | 10 +- src/drivers/spi/gigadevice.c | 10 +- src/drivers/spi/winbond.c | 10 +- src/drivers/ti/tps65090/tps65090.c | 2 +- src/drivers/uart/uart8250mem.c | 4 +- src/ec/google/chromeec/crosec_proto.c | 20 +- src/ec/google/chromeec/ec.c | 18 +- src/ec/google/chromeec/ec_i2c.c | 30 +-- src/ec/google/chromeec/ec_spi.c | 8 +- src/lib/bootmem.c | 6 +- src/lib/cbfs.c | 10 +- src/lib/cbfs_core.c | 4 +- src/lib/cbmem.c | 16 +- src/lib/compute_ip_checksum.c | 6 +- src/lib/coreboot_table.c | 12 +- src/lib/edid.c | 2 +- src/lib/gcov-glue.c | 2 +- src/lib/generic_sdram.c | 2 +- src/lib/hexdump.c | 4 +- src/lib/loaders/cbfs_ramstage_loader.c | 4 +- src/lib/loaders/load_and_run_ramstage.c | 2 +- src/lib/ramstage_cache.c | 14 +- src/lib/ramtest.c | 4 +- src/lib/reg_script.c | 22 +- src/lib/timestamp.c | 4 +- src/lib/trace.c | 2 +- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 15 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +- src/mainboard/apple/macbook21/romstage.c | 4 +- src/mainboard/arima/hdama/mptable.c | 4 +- src/mainboard/arima/hdama/romstage.c | 2 +- src/mainboard/asus/a8n_e/irq_tables.c | 14 +- src/mainboard/asus/a8n_e/mptable.c | 2 +- src/mainboard/asus/a8n_e/romstage.c | 6 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 4 +- src/mainboard/asus/a8v-e_se/romstage.c | 4 +- src/mainboard/asus/k8v-x/romstage.c | 4 +- src/mainboard/asus/m2v-mx_se/romstage.c | 4 +- src/mainboard/asus/m2v/romstage.c | 4 +- src/mainboard/bifferos/bifferboard/romstage.c | 2 +- src/mainboard/broadcom/blast/irq_tables.c | 15 +- src/mainboard/broadcom/blast/mptable.c | 2 +- src/mainboard/broadcom/blast/romstage.c | 2 +- src/mainboard/emulation/qemu-i440fx/fw_cfg.c | 28 +-- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/bootblock.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- src/mainboard/emulation/qemu-riscv/uart.c | 2 +- src/mainboard/getac/p470/romstage.c | 4 +- src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c | 19 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 6 +- src/mainboard/gigabyte/m57sli/fanctl.c | 6 +- src/mainboard/gigabyte/m57sli/irq_tables.c | 15 +- src/mainboard/gigabyte/m57sli/romstage.c | 6 +- src/mainboard/google/daisy/chromeos.c | 2 +- src/mainboard/google/nyan/boardid.c | 2 +- src/mainboard/google/nyan/chromeos.c | 2 +- src/mainboard/google/nyan/mainboard.c | 2 +- src/mainboard/google/nyan/pmic.c | 2 +- src/mainboard/google/nyan/romstage.c | 6 +- src/mainboard/google/nyan/sdram_configs.c | 2 +- src/mainboard/google/nyan_big/boardid.c | 2 +- src/mainboard/google/nyan_big/chromeos.c | 2 +- src/mainboard/google/nyan_big/mainboard.c | 2 +- src/mainboard/google/nyan_big/pmic.c | 2 +- src/mainboard/google/nyan_big/romstage.c | 6 +- src/mainboard/google/nyan_big/sdram_configs.c | 2 +- src/mainboard/google/nyan_blaze/boardid.c | 2 +- src/mainboard/google/nyan_blaze/chromeos.c | 2 +- src/mainboard/google/nyan_blaze/mainboard.c | 2 +- src/mainboard/google/nyan_blaze/pmic.c | 2 +- src/mainboard/google/nyan_blaze/romstage.c | 6 +- src/mainboard/google/nyan_blaze/sdram_configs.c | 2 +- src/mainboard/google/peach_pit/chromeos.c | 2 +- src/mainboard/google/peach_pit/mainboard.c | 2 +- src/mainboard/google/peach_pit/romstage.c | 8 +- src/mainboard/google/rambi/chromeos.c | 2 +- src/mainboard/google/rambi/mainboard_smi.c | 14 +- src/mainboard/google/rambi/romstage.c | 2 +- src/mainboard/google/samus/spd.c | 2 +- src/mainboard/hp/dl145_g1/irq_tables.c | 15 +- src/mainboard/hp/dl145_g1/romstage.c | 2 +- src/mainboard/hp/dl145_g3/mptable.c | 6 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 6 +- .../hp/pavilion_m6_1035dx/mainboard_smi.c | 10 +- src/mainboard/ibase/mb899/romstage.c | 4 +- src/mainboard/intel/bayleybay_fsp/romstage.c | 6 +- src/mainboard/intel/d810e2cb/gpio.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 4 +- src/mainboard/intel/eagleheights/mptable.c | 2 +- src/mainboard/intel/minnowmax/romstage.c | 2 +- src/mainboard/intel/mohonpeak/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/acpi_tables.c | 6 +- src/mainboard/iwill/dk8_htx/irq_tables.c | 15 +- src/mainboard/iwill/dk8_htx/romstage.c | 2 +- src/mainboard/iwill/dk8s2/romstage.c | 2 +- src/mainboard/iwill/dk8x/romstage.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 14 +- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 4 +- src/mainboard/kontron/986lcd-m/romstage.c | 4 +- src/mainboard/lenovo/g505s/mainboard_smi.c | 10 +- src/mainboard/lenovo/t60/romstage.c | 4 +- src/mainboard/lenovo/x60/romstage.c | 4 +- src/mainboard/msi/ms7135/irq_tables.c | 16 +- src/mainboard/msi/ms7260/irq_tables.c | 16 +- src/mainboard/msi/ms7260/mptable.c | 2 +- src/mainboard/msi/ms7260/romstage.c | 6 +- src/mainboard/msi/ms9185/irq_tables.c | 15 +- src/mainboard/msi/ms9185/mptable.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/mainboard/msi/ms9282/irq_tables.c | 15 +- src/mainboard/msi/ms9282/mptable.c | 2 +- src/mainboard/msi/ms9282/romstage.c | 6 +- src/mainboard/msi/ms9652_fam10/irq_tables.c | 15 +- src/mainboard/msi/ms9652_fam10/mptable.c | 2 +- src/mainboard/newisys/khepri/romstage.c | 2 +- src/mainboard/nvidia/l1_2pvv/irq_tables.c | 15 +- src/mainboard/nvidia/l1_2pvv/mptable.c | 2 +- src/mainboard/nvidia/l1_2pvv/romstage.c | 6 +- src/mainboard/rca/rm4100/gpio.c | 4 +- src/mainboard/roda/rk886ex/romstage.c | 4 +- src/mainboard/roda/rk9/ti_pci7xx1.c | 2 +- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/mainboard/sunw/ultra40/irq_tables.c | 15 +- src/mainboard/sunw/ultra40/mptable.c | 2 +- src/mainboard/sunw/ultra40/romstage.c | 6 +- src/mainboard/supermicro/h8dme/irq_tables.c | 15 +- src/mainboard/supermicro/h8dme/mptable.c | 2 +- src/mainboard/supermicro/h8dme/romstage.c | 6 +- src/mainboard/supermicro/h8dmr/irq_tables.c | 15 +- src/mainboard/supermicro/h8dmr/mptable.c | 2 +- src/mainboard/supermicro/h8dmr/romstage.c | 6 +- src/mainboard/supermicro/h8dmr_fam10/irq_tables.c | 15 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 4 +- src/mainboard/supermicro/h8qme_fam10/irq_tables.c | 15 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 +- src/mainboard/technexion/tim5690/mainboard.c | 2 +- src/mainboard/technexion/tim5690/speaker.c | 2 +- src/mainboard/technexion/tim5690/tn_post_code.c | 6 +- src/mainboard/thomson/ip1000/gpio.c | 4 +- src/mainboard/ti/beaglebone/bootblock.c | 10 +- src/mainboard/tyan/s2850/mptable.c | 2 +- src/mainboard/tyan/s2875/mptable.c | 2 +- src/mainboard/tyan/s2880/mptable.c | 2 +- src/mainboard/tyan/s2881/irq_tables.c | 15 +- src/mainboard/tyan/s2881/romstage.c | 2 +- src/mainboard/tyan/s2882/irq_tables.c | 17 +- src/mainboard/tyan/s2882/mptable.c | 2 +- src/mainboard/tyan/s2885/irq_tables.c | 15 +- src/mainboard/tyan/s2885/romstage.c | 2 +- src/mainboard/tyan/s2891/irq_tables.c | 15 +- src/mainboard/tyan/s2891/mptable.c | 2 +- src/mainboard/tyan/s2891/romstage.c | 6 +- src/mainboard/tyan/s2892/irq_tables.c | 15 +- src/mainboard/tyan/s2892/mptable.c | 2 +- src/mainboard/tyan/s2892/romstage.c | 6 +- src/mainboard/tyan/s2895/irq_tables.c | 15 +- src/mainboard/tyan/s2895/mptable.c | 2 +- src/mainboard/tyan/s2912/irq_tables.c | 15 +- src/mainboard/tyan/s2912/mptable.c | 2 +- src/mainboard/tyan/s2912/romstage.c | 6 +- src/mainboard/tyan/s2912_fam10/irq_tables.c | 15 +- src/mainboard/tyan/s2912_fam10/mptable.c | 2 +- src/mainboard/tyan/s2912_fam10/romstage.c | 4 +- src/mainboard/tyan/s4880/mptable.c | 2 +- src/mainboard/tyan/s4882/mptable.c | 2 +- src/mainboard/tyan/s4882/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/mainboard/winent/mb6047/irq_tables.c | 15 +- src/mainboard/winent/mb6047/mptable.c | 2 +- src/mainboard/winent/mb6047/romstage.c | 6 +- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 4 +- src/northbridge/amd/agesa/family14/northbridge.c | 4 +- src/northbridge/amd/agesa/family15/northbridge.c | 4 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 6 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 6 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 6 +- src/northbridge/amd/amdfam10/acpi.c | 2 +- src/northbridge/amd/amdfam10/northbridge.c | 2 +- src/northbridge/amd/amdk8/acpi.c | 4 +- src/northbridge/amd/amdk8/coherent_ht.c | 81 +++---- src/northbridge/amd/amdk8/debug.c | 21 +- src/northbridge/amd/amdk8/early_ht.c | 14 +- src/northbridge/amd/amdk8/f_pci.c | 17 +- src/northbridge/amd/amdk8/get_sblk_pci1234.c | 4 +- src/northbridge/amd/amdk8/incoherent_ht.c | 134 ++++++------ src/northbridge/amd/amdk8/misc_control.c | 8 +- src/northbridge/amd/amdk8/northbridge.c | 2 +- src/northbridge/amd/amdk8/raminit.c | 132 +++++------ src/northbridge/amd/amdk8/raminit_f.c | 144 ++++++------ src/northbridge/amd/amdk8/raminit_f_dqs.c | 141 ++++++------ src/northbridge/amd/amdk8/raminit_test.c | 22 +- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 16 +- src/northbridge/amd/gx2/grphinit.c | 2 +- src/northbridge/amd/gx2/northbridge.c | 2 +- src/northbridge/amd/gx2/northbridgeinit.c | 40 ++-- src/northbridge/amd/gx2/raminit.c | 34 +-- src/northbridge/amd/lx/grphinit.c | 2 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/northbridgeinit.c | 40 ++-- src/northbridge/amd/lx/raminit.c | 36 +-- src/northbridge/amd/pi/00730F01/northbridge.c | 8 +- src/northbridge/dmp/vortex86ex/northbridge.c | 2 +- src/northbridge/intel/e7501/debug.c | 8 +- src/northbridge/intel/e7501/northbridge.c | 4 +- src/northbridge/intel/e7501/raminit.c | 154 ++++++------- src/northbridge/intel/e7501/reset_test.c | 2 +- src/northbridge/intel/e7505/debug.c | 8 +- src/northbridge/intel/e7505/northbridge.c | 4 +- src/northbridge/intel/e7505/raminit.c | 154 ++++++------- src/northbridge/intel/fsp_rangeley/northbridge.c | 4 +- .../intel/fsp_sandybridge/northbridge.c | 14 +- src/northbridge/intel/gm45/bootblock.c | 2 +- src/northbridge/intel/gm45/gma.c | 4 +- src/northbridge/intel/haswell/bootblock.c | 2 +- src/northbridge/intel/haswell/northbridge.c | 12 +- src/northbridge/intel/i3100/raminit.c | 4 +- src/northbridge/intel/i3100/reset_test.c | 2 +- src/northbridge/intel/i440bx/northbridge.c | 2 +- src/northbridge/intel/i440bx/raminit.c | 12 +- src/northbridge/intel/i440lx/northbridge.c | 2 +- src/northbridge/intel/i440lx/raminit.c | 8 +- src/northbridge/intel/i5000/northbridge.c | 8 +- src/northbridge/intel/i82810/northbridge.c | 2 +- src/northbridge/intel/i82830/northbridge.c | 2 +- src/northbridge/intel/i855/debug.c | 4 +- src/northbridge/intel/i855/northbridge.c | 2 +- src/northbridge/intel/i855/raminit.c | 58 ++--- src/northbridge/intel/i855/reset_test.c | 2 +- src/northbridge/intel/i945/bootblock.c | 2 +- src/northbridge/intel/i945/debug.c | 4 +- src/northbridge/intel/i945/northbridge.c | 14 +- src/northbridge/intel/nehalem/gma.c | 4 +- src/northbridge/intel/nehalem/northbridge.c | 10 +- src/northbridge/intel/sandybridge/bootblock.c | 2 +- .../intel/sandybridge/gma_ivybridge_lvds.c | 4 +- .../intel/sandybridge/gma_sandybridge_lvds.c | 4 +- src/northbridge/intel/sandybridge/northbridge.c | 14 +- src/northbridge/intel/sandybridge/raminit_native.c | 2 +- src/northbridge/intel/sch/northbridge.c | 4 +- src/northbridge/via/vx800/early_serial.c | 8 +- src/northbridge/via/vx800/examples/romstage.c | 4 +- src/northbridge/via/vx800/translator_ddr2_init.c | 4 +- src/northbridge/via/vx800/vga.c | 2 +- src/northbridge/via/vx900/chrome9hd.c | 2 +- src/northbridge/via/vx900/northbridge.c | 6 +- src/northbridge/via/vx900/pci_util.c | 12 +- src/soc/intel/baytrail/acpi.c | 4 +- src/soc/intel/baytrail/bootblock/bootblock.c | 4 +- src/soc/intel/baytrail/cpu.c | 12 +- src/soc/intel/baytrail/elog.c | 6 +- src/soc/intel/baytrail/gfx.c | 2 +- src/soc/intel/baytrail/gpio.c | 2 +- src/soc/intel/baytrail/hda.c | 2 +- src/soc/intel/baytrail/iosf.c | 102 ++++----- src/soc/intel/baytrail/lpe.c | 2 +- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pcie.c | 8 +- src/soc/intel/baytrail/pmutil.c | 102 ++++----- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/refcode.c | 4 +- src/soc/intel/baytrail/romstage/gfx.c | 4 +- src/soc/intel/baytrail/romstage/pmc.c | 6 +- src/soc/intel/baytrail/romstage/raminit.c | 12 +- src/soc/intel/baytrail/romstage/romstage.c | 26 +-- src/soc/intel/baytrail/romstage/uart.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- src/soc/intel/baytrail/smihandler.c | 24 +- src/soc/intel/baytrail/smm.c | 14 +- src/soc/intel/baytrail/southcluster.c | 12 +- src/soc/intel/baytrail/spi.c | 150 ++++++------- src/soc/intel/broadwell/acpi.c | 4 +- src/soc/intel/broadwell/bootblock/systemagent.c | 2 +- src/soc/intel/broadwell/monotonic_timer.c | 8 +- src/soc/intel/broadwell/ramstage.c | 2 +- src/soc/intel/broadwell/refcode.c | 4 +- src/soc/intel/broadwell/romstage/romstage.c | 10 +- src/soc/intel/broadwell/romstage/stack.c | 10 +- src/soc/intel/broadwell/spi.c | 156 ++++++------- src/soc/intel/broadwell/systemagent.c | 12 +- src/soc/intel/common/mrc_cache.c | 6 +- src/soc/intel/common/nvm.c | 6 +- src/soc/intel/fsp_baytrail/acpi.c | 2 +- src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 10 +- src/soc/intel/fsp_baytrail/cpu.c | 10 +- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 2 +- src/soc/intel/fsp_baytrail/gpio.c | 22 +- src/soc/intel/fsp_baytrail/iosf.c | 30 +-- src/soc/intel/fsp_baytrail/northcluster.c | 8 +- src/soc/intel/fsp_baytrail/nvm.c | 6 +- src/soc/intel/fsp_baytrail/pmutil.c | 102 ++++----- src/soc/intel/fsp_baytrail/romstage/pmc.c | 2 +- .../intel/fsp_baytrail/romstage/report_platform.c | 10 +- src/soc/intel/fsp_baytrail/romstage/romstage.c | 28 +-- src/soc/intel/fsp_baytrail/romstage/uart.c | 2 +- src/soc/intel/fsp_baytrail/smihandler.c | 24 +- src/soc/intel/fsp_baytrail/smm.c | 12 +- src/soc/intel/fsp_baytrail/southcluster.c | 22 +- src/soc/intel/fsp_baytrail/spi.c | 150 ++++++------- src/soc/nvidia/tegra/i2c.c | 20 +- src/soc/nvidia/tegra/pingroup.c | 6 +- src/soc/nvidia/tegra/pinmux.c | 6 +- src/soc/nvidia/tegra124/clock.c | 8 +- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c | 122 +++++------ src/soc/nvidia/tegra124/power.c | 8 +- src/soc/nvidia/tegra124/sdram.c | 16 +- src/soc/nvidia/tegra124/uart.c | 24 +- src/soc/qualcomm/ipq806x/spi.c | 16 +- src/soc/qualcomm/ipq806x/uart.c | 6 +- src/soc/samsung/exynos5250/cpu.c | 6 +- src/soc/samsung/exynos5250/i2c.c | 28 +-- src/soc/samsung/exynos5250/mct.c | 6 +- src/soc/samsung/exynos5250/monotonic_timer.c | 2 +- src/soc/samsung/exynos5250/power.c | 2 +- src/soc/samsung/exynos5250/spi.c | 2 +- src/soc/samsung/exynos5250/wakeup.c | 2 +- src/soc/samsung/exynos5420/cpu.c | 6 +- src/soc/samsung/exynos5420/i2c.c | 112 +++++----- src/soc/samsung/exynos5420/mct.c | 6 +- src/soc/samsung/exynos5420/monotonic_timer.c | 2 +- src/soc/samsung/exynos5420/power.c | 2 +- src/soc/samsung/exynos5420/smp.c | 36 +-- src/soc/samsung/exynos5420/spi.c | 22 +- src/soc/samsung/exynos5420/wakeup.c | 2 +- src/southbridge/amd/agesa/hudson/early_setup.c | 2 +- src/southbridge/amd/agesa/hudson/hudson.c | 4 +- src/southbridge/amd/agesa/hudson/smi.c | 2 +- src/southbridge/amd/agesa/hudson/smi_util.c | 12 +- src/southbridge/amd/agesa/hudson/smihandler.c | 20 +- src/southbridge/amd/agesa/hudson/spi.c | 12 +- src/southbridge/amd/amd8111/acpi.c | 17 +- src/southbridge/amd/amd8111/amd8111.c | 2 +- src/southbridge/amd/amd8111/early_ctrl.c | 2 +- src/southbridge/amd/amd8111/early_smbus.c | 2 +- src/southbridge/amd/amd8111/ide.c | 4 +- src/southbridge/amd/amd8111/lpc.c | 2 +- src/southbridge/amd/amd8111/pci.c | 2 +- src/southbridge/amd/amd8131-disable/bridge.c | 6 +- src/southbridge/amd/amd8131/bridge.c | 8 +- src/southbridge/amd/amd8132/bridge.c | 8 +- src/southbridge/amd/amd8151/agp3.c | 4 +- src/southbridge/amd/cimx/sb700/lpc.c | 2 +- src/southbridge/amd/cimx/sb800/cfg.c | 2 +- src/southbridge/amd/cs5535/chipsetinit.c | 2 +- src/southbridge/amd/cs5535/early_setup.c | 2 +- src/southbridge/amd/cs5536/early_setup.c | 2 +- src/southbridge/amd/cs5536/ide.c | 2 +- src/southbridge/amd/pi/avalon/early_setup.c | 2 +- src/southbridge/amd/pi/avalon/hudson.c | 4 +- src/southbridge/amd/pi/avalon/smi.c | 2 +- src/southbridge/amd/pi/avalon/smi_util.c | 12 +- src/southbridge/amd/pi/avalon/smihandler.c | 20 +- src/southbridge/amd/rs690/cmn.c | 2 +- src/southbridge/amd/rs780/cmn.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/broadcom/bcm21000/pcie.c | 4 +- src/southbridge/broadcom/bcm5780/pcie.c | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 16 +- src/southbridge/broadcom/bcm5785/lpc.c | 2 +- src/southbridge/broadcom/bcm5785/sata.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 10 +- src/southbridge/broadcom/bcm5785/usb.c | 2 +- src/southbridge/intel/bd82x6x/pci.c | 4 +- src/southbridge/intel/bd82x6x/smi.c | 2 +- src/southbridge/intel/common/spi.c | 222 +++++++++---------- src/southbridge/intel/esb6300/ehci.c | 4 +- src/southbridge/intel/esb6300/esb6300.c | 4 +- src/southbridge/intel/esb6300/lpc.c | 16 +- src/southbridge/intel/esb6300/pci.c | 2 +- src/southbridge/intel/esb6300/pic.c | 2 +- src/southbridge/intel/esb6300/uhci.c | 2 +- src/southbridge/intel/fsp_bd82x6x/smi.c | 2 +- src/southbridge/intel/fsp_rangeley/early_init.c | 4 +- src/southbridge/intel/fsp_rangeley/lpc.c | 14 +- src/southbridge/intel/fsp_rangeley/romstage.c | 4 +- src/southbridge/intel/fsp_rangeley/spi.c | 242 ++++++++++----------- src/southbridge/intel/i82801ax/lpc.c | 10 +- src/southbridge/intel/i82801bx/lpc.c | 16 +- src/southbridge/intel/i82801cx/i82801cx.c | 4 +- src/southbridge/intel/i82801cx/ide.c | 2 +- src/southbridge/intel/i82801cx/lpc.c | 10 +- src/southbridge/intel/i82801cx/pci.c | 2 +- src/southbridge/intel/i82801dx/i82801dx.c | 4 +- src/southbridge/intel/i82801dx/ide.c | 2 +- src/southbridge/intel/i82801dx/pci.c | 2 +- src/southbridge/intel/i82801dx/smi.c | 2 +- src/southbridge/intel/i82801ex/ehci.c | 4 +- src/southbridge/intel/i82801ex/i82801ex.c | 4 +- src/southbridge/intel/i82801ex/lpc.c | 16 +- src/southbridge/intel/i82801ex/pci.c | 2 +- src/southbridge/intel/i82801ex/uhci.c | 2 +- src/southbridge/intel/i82801gx/pci.c | 4 +- src/southbridge/intel/i82801gx/smi.c | 2 +- src/southbridge/intel/i82801ix/smi.c | 2 +- src/southbridge/intel/i82870/ioapic.c | 12 +- src/southbridge/intel/i82870/pci_parity.c | 2 +- src/southbridge/intel/ibexpeak/smi.c | 2 +- src/southbridge/intel/lynxpoint/pci.c | 4 +- src/southbridge/intel/sch/smi.c | 2 +- src/southbridge/rdc/r8610/bootblock.c | 2 +- src/southbridge/sis/sis966/early_setup_car.c | 6 +- src/southbridge/sis/sis966/early_smbus.c | 32 +-- src/southbridge/sis/sis966/ide.c | 10 +- src/southbridge/sis/sis966/lpc.c | 16 +- src/southbridge/sis/sis966/pcie.c | 2 +- src/southbridge/sis/sis966/sata.c | 8 +- src/southbridge/sis/sis966/sis966.c | 18 +- src/southbridge/sis/sis966/usb.c | 4 +- src/southbridge/via/k8t890/chrome.c | 2 +- src/southbridge/via/k8t890/host_ctrl.c | 2 +- src/southbridge/via/vt8235/early_serial.c | 8 +- src/southbridge/via/vt8235/nic.c | 2 +- src/southbridge/via/vt82c686/early_serial.c | 4 +- src/superio/smsc/fdc37m60x/early_serial.c | 2 +- src/vendorcode/amd/agesa/f10/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f12/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f14/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f15/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c | 2 +- src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c | 2 +- src/vendorcode/google/chromeos/cros_vpd.c | 24 +- src/vendorcode/google/chromeos/gnvs.c | 2 +- src/vendorcode/google/chromeos/vbnv_cmos.c | 14 +- src/vendorcode/google/chromeos/vbnv_ec.c | 16 +- src/vendorcode/google/chromeos/vboot_handoff.c | 2 +- src/vendorcode/google/chromeos/vboot_loader.c | 14 +- src/vendorcode/google/chromeos/vboot_wrapper.c | 26 +-- src/vendorcode/google/chromeos/vpd_decode.c | 22 +- src/vendorcode/intel/fsp/baytrail/srx/board_fsp.c | 27 +-- 498 files changed, 3092 insertions(+), 2994 deletions(-)
diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index 31819f7..b3afcd9 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -54,7 +54,7 @@ enum dcache_op {
unsigned int dcache_line_bytes(void) { - uint32_t ccsidr; + u32 ccsidr; static unsigned int line_bytes = 0;
if (line_bytes) @@ -79,7 +79,7 @@ static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op) unsigned long line, linesize;
linesize = dcache_line_bytes(); - line = (uint32_t)addr & ~(linesize - 1); + line = (u32)addr & ~(linesize - 1);
dsb(); while ((void *)line < addr + len) { @@ -123,7 +123,7 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) */ void dcache_mmu_disable(void) { - uint32_t sctlr; + u32 sctlr;
dcache_clean_invalidate_all(); sctlr = read_sctlr(); @@ -133,7 +133,7 @@ void dcache_mmu_disable(void)
void dcache_mmu_enable(void) { - uint32_t sctlr; + u32 sctlr;
sctlr = read_sctlr(); sctlr |= SCTLR_C | SCTLR_M; diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index b02e5c1..9bfb1dd 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -33,22 +33,22 @@ #include <arch/exception.h> #include <console/console.h>
-uint8_t exception_stack[0x100] __attribute__((aligned(8))); +u8 exception_stack[0x100] __attribute__((aligned(8))); extern void *exception_stack_end;
-void exception_undefined_instruction(uint32_t *); -void exception_software_interrupt(uint32_t *); -void exception_prefetch_abort(uint32_t *); -void exception_data_abort(uint32_t *); -void exception_not_used(uint32_t *); -void exception_irq(uint32_t *); -void exception_fiq(uint32_t *); +void exception_undefined_instruction(u32 *); +void exception_software_interrupt(u32 *); +void exception_prefetch_abort(u32 *); +void exception_data_abort(u32 *); +void exception_not_used(u32 *); +void exception_irq(u32 *); +void exception_fiq(u32 *);
static void dump_stack(uintptr_t addr, size_t bytes) { int i, j; const int line = 8; - uint32_t *ptr = (uint32_t *)(addr & ~(line * sizeof(*ptr) - 1)); + u32 *ptr = (u32 *)(addr & ~(line * sizeof(*ptr) - 1));
printk(BIOS_ERR, "Dumping stack:\n"); for (i = bytes / sizeof(*ptr); i >= 0; i -= line) { @@ -59,7 +59,7 @@ static void dump_stack(uintptr_t addr, size_t bytes) } }
-static void print_regs(uint32_t *regs) +static void print_regs(u32 *regs) { int i;
@@ -78,7 +78,7 @@ static void print_regs(uint32_t *regs) } }
-void exception_undefined_instruction(uint32_t *regs) +void exception_undefined_instruction(u32 *regs) { printk(BIOS_ERR, "exception _undefined_instruction\n"); print_regs(regs); @@ -86,7 +86,7 @@ void exception_undefined_instruction(uint32_t *regs) die("exception"); }
-void exception_software_interrupt(uint32_t *regs) +void exception_software_interrupt(u32 *regs) { printk(BIOS_ERR, "exception _software_interrupt\n"); print_regs(regs); @@ -94,7 +94,7 @@ void exception_software_interrupt(uint32_t *regs) die("exception"); }
-void exception_prefetch_abort(uint32_t *regs) +void exception_prefetch_abort(u32 *regs) { printk(BIOS_ERR, "exception _prefetch_abort\n"); print_regs(regs); @@ -102,7 +102,7 @@ void exception_prefetch_abort(uint32_t *regs) die("exception"); }
-void exception_data_abort(uint32_t *regs) +void exception_data_abort(u32 *regs) { printk(BIOS_ERR, "exception _data_abort\n"); print_regs(regs); @@ -110,7 +110,7 @@ void exception_data_abort(uint32_t *regs) die("exception"); }
-void exception_not_used(uint32_t *regs) +void exception_not_used(u32 *regs) { printk(BIOS_ERR, "exception _not_used\n"); print_regs(regs); @@ -118,7 +118,7 @@ void exception_not_used(uint32_t *regs) die("exception"); }
-void exception_irq(uint32_t *regs) +void exception_irq(u32 *regs) { printk(BIOS_ERR, "exception _irq\n"); print_regs(regs); @@ -126,7 +126,7 @@ void exception_irq(uint32_t *regs) die("exception"); }
-void exception_fiq(uint32_t *regs) +void exception_fiq(u32 *regs) { printk(BIOS_ERR, "exception _fiq\n"); print_regs(regs); @@ -136,7 +136,7 @@ void exception_fiq(uint32_t *regs)
void exception_init(void) { - uint32_t sctlr = read_sctlr(); + u32 sctlr = read_sctlr(); /* Handle exceptions in ARM mode. */ sctlr &= ~SCTLR_TE; /* Set V=0 in SCTLR so VBAR points to the exception vector table. */ @@ -144,7 +144,7 @@ void exception_init(void) /* Enforce alignment temporarily. */ write_sctlr(sctlr);
- extern uint32_t exception_table[]; + extern u32 exception_table[]; set_vbar((uintptr_t)exception_table); exception_stack_end = exception_stack + sizeof(exception_stack);
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 1b5957c..bee4329 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -57,8 +57,8 @@
#define BLOCK_SHIFT 21
-typedef uint64_t pgd_t; -typedef uint64_t pmd_t; +typedef u64 pgd_t; +typedef u64 pmd_t; static const unsigned int denom = 2; #else /* CONFIG_ARM_LPAE */ /* @@ -84,8 +84,8 @@ static const unsigned int denom = 2;
#define BLOCK_SHIFT 20
-typedef uint32_t pgd_t; -typedef uint32_t pmd_t; +typedef u32 pgd_t; +typedef u32 pmd_t; static const unsigned int denom = 1; #endif /* CONFIG_ARM_LPAE */
@@ -212,7 +212,7 @@ void mmu_init(void) * See B3.6.1 of ARMv7 Architecture Reference Manual */ for (i = 0; i < 4; i++) { - pgd_buff[i] = ((uint32_t)pmd & PAGE_MASK) | + pgd_buff[i] = ((u32)pmd & PAGE_MASK) | 3; /* 0b11: valid table entry */ pmd += BLOCK_SIZE / PAGE_SIZE; } diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 20c5a9f..f0a6602 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -30,7 +30,7 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
#if !CONFIG_DYNAMIC_CBMEM -void __attribute__((weak)) get_cbmem_table(uint64_t *base, uint64_t *size) +void __attribute__((weak)) get_cbmem_table(u64 *base, u64 *size) { printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_table for your board\n"); *base = 0; diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index a0eff46..e5c759f 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -45,7 +45,7 @@ void tlb_invalidate_all(void)
unsigned int dcache_line_bytes(void) { - uint32_t ccsidr; + u32 ccsidr; static unsigned int line_bytes = 0;
if (line_bytes) @@ -54,7 +54,7 @@ unsigned int dcache_line_bytes(void) ccsidr = read_ccsidr(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 4 */ line_bytes = 1 << ((ccsidr & 0x7) + 4); /* words per line */ - line_bytes *= sizeof(uint32_t); /* bytes per word */ + line_bytes *= sizeof(u32); /* bytes per word */
return line_bytes; } @@ -75,10 +75,10 @@ enum dcache_op { */ static void dcache_op_va(void const *addr, size_t len, enum dcache_op op) { - uint64_t line, linesize; + u64 line, linesize;
linesize = dcache_line_bytes(); - line = (uint64_t)addr & ~(linesize - 1); + line = (u64)addr & ~(linesize - 1);
dsb(); while ((void *)line < addr + len) { @@ -122,7 +122,7 @@ void dcache_invalidate_by_va(void const *addr, size_t len) */ void dcache_mmu_disable(void) { - uint32_t sctlr; + u32 sctlr;
flush_dcache_all(); sctlr = read_sctlr(current_el()); @@ -132,7 +132,7 @@ void dcache_mmu_disable(void)
void dcache_mmu_enable(void) { - uint32_t sctlr; + u32 sctlr;
sctlr = read_sctlr(current_el()); sctlr |= SCTLR_C | SCTLR_M; diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index 31e3131..515c474 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -33,16 +33,16 @@ #include <arch/exception.h> #include <console/console.h>
-void exception_sync_el0(uint64_t *regs, uint64_t esr); -void exception_irq_el0(uint64_t *regs, uint64_t esr); -void exception_fiq_el0(uint64_t *regs, uint64_t esr); -void exception_serror_el0(uint64_t *regs, uint64_t esr); -void exception_sync(uint64_t *regs, uint64_t esr); -void exception_irq(uint64_t *regs, uint64_t esr); -void exception_fiq(uint64_t *regs, uint64_t esr); -void exception_serror(uint64_t *regs, uint64_t esr); - -static void print_regs(uint64_t *regs) +void exception_sync_el0(u64 *regs, u64 esr); +void exception_irq_el0(u64 *regs, u64 esr); +void exception_fiq_el0(u64 *regs, u64 esr); +void exception_serror_el0(u64 *regs, u64 esr); +void exception_sync(u64 *regs, u64 esr); +void exception_irq(u64 *regs, u64 esr); +void exception_fiq(u64 *regs, u64 esr); +void exception_serror(u64 *regs, u64 esr); + +static void print_regs(u64 *regs) { int i;
@@ -56,56 +56,56 @@ static void print_regs(uint64_t *regs) } }
-void exception_sync_el0(uint64_t *regs, uint64_t esr) +void exception_sync_el0(u64 *regs, u64 esr) { printk(BIOS_ERR, "exception _sync_el0 (ESR = 0x%08llx)\n", esr); print_regs(regs); die("exception"); }
-void exception_irq_el0(uint64_t *regs, uint64_t esr) +void exception_irq_el0(u64 *regs, u64 esr) { printk(BIOS_ERR, "exception _irq_el0 (ESR = 0x%08llx)\n", esr); print_regs(regs); die("exception"); }
-void exception_fiq_el0(uint64_t *regs, uint64_t esr) +void exception_fiq_el0(u64 *regs, u64 esr) { printk(BIOS_ERR, "exception _fiq_el0 (ESR = 0x%08llx)\n", esr); print_regs(regs); die("exception"); }
-void exception_serror_el0(uint64_t *regs, uint64_t esr) +void exception_serror_el0(u64 *regs, u64 esr) { printk(BIOS_ERR, "exception _serror_el0 (ESR = 0x%08llx)\n", esr); print_regs(regs); die("exception"); }
-void exception_sync(uint64_t *regs, uint64_t esr) +void exception_sync(u64 *regs, u64 esr) { printk(BIOS_ERR, "exception _sync (ESR = 0x%08llx)\n", esr); print_regs(regs); die("exception"); }
-void exception_irq(uint64_t *regs, uint64_t esr) +void exception_irq(u64 *regs, u64 esr) { printk(BIOS_ERR, "exception _irq (ESR = 0x%08llx)\n", esr); print_regs(regs); die("exception"); }
-void exception_fiq(uint64_t *regs, uint64_t esr) +void exception_fiq(u64 *regs, u64 esr) { printk(BIOS_ERR, "exception _fiq (ESR = 0x%08llx)\n", esr); print_regs(regs); die("exception"); }
-void exception_serror(uint64_t *regs, uint64_t esr) +void exception_serror(u64 *regs, u64 esr) { printk(BIOS_ERR, "exception _serror (ESR = 0x%08llx)\n", esr); print_regs(regs); @@ -122,7 +122,7 @@ void exception_init(void) /* Enforce alignment temporarily. */ //write_sctlr(sctlr);
- extern uint32_t exception_table[]; + extern u32 exception_table[]; set_vbar((uintptr_t)exception_table);
printk(BIOS_DEBUG, "Exception handlers installed.\n"); diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index 49fab9f..c36b80b 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -34,8 +34,8 @@ * TODO: "High" tables are a convention used on x86. Maybe we can * clean up that naming at some point. */ -uint64_t high_tables_base = 0; -uint64_t high_tables_size; +u64 high_tables_base = 0; +u64 high_tables_size; #endif
void cbmem_arch_init(void) diff --git a/src/arch/arm64/timestamp.c b/src/arch/arm64/timestamp.c index e6a8159..d68e609 100644 --- a/src/arch/arm64/timestamp.c +++ b/src/arch/arm64/timestamp.c @@ -20,10 +20,10 @@ #include <timestamp.h> #include <timer.h>
-uint64_t timestamp_get(void) +u64 timestamp_get(void) { struct mono_time timestamp; timer_monotonic_get(×tamp); - return (uint64_t)timestamp.microseconds; + return (u64)timestamp.microseconds; }
diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c index 8e858cb..459eca1 100644 --- a/src/arch/riscv/rom_media.c +++ b/src/arch/riscv/rom_media.c @@ -71,7 +71,7 @@ static int init_rom_media_cbfs(struct cbfs_media *media) { printk(BIOS_ERR, "Expected %08lx and got %08lx\n", (unsigned long) CBFS_HEADER_MAGIC, (unsigned long) ntohl(header->magic)); return -1; } else { - uint32_t romsize = ntohl(header->romsize); + u32 romsize = ntohl(header->romsize); media->context = (void*)(uintptr_t)romsize; #if defined(CONFIG_ROM_SIZE) if (CONFIG_ROM_SIZE != romsize) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 8e7ce46..7ced437 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -115,7 +115,7 @@ int acpigen_write_dword(unsigned int data) return 5; }
-int acpigen_write_qword(uint64_t data) +int acpigen_write_qword(u64 data) { /* qword op */ acpigen_emit_byte(0xe); @@ -130,7 +130,7 @@ int acpigen_write_qword(uint64_t data) return 9; }
-int acpigen_write_name_byte(const char *name, uint8_t val) +int acpigen_write_name_byte(const char *name, u8 val) { int len; len = acpigen_write_name(name); @@ -138,7 +138,7 @@ int acpigen_write_name_byte(const char *name, uint8_t val) return len; }
-int acpigen_write_name_dword(const char *name, uint32_t val) +int acpigen_write_name_dword(const char *name, u32 val) { int len; len = acpigen_write_name(name); @@ -146,7 +146,7 @@ int acpigen_write_name_dword(const char *name, uint32_t val) return len; }
-int acpigen_write_name_qword(const char *name, uint64_t val) +int acpigen_write_name_qword(const char *name, u64 val) { int len; len = acpigen_write_name(name); diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 8b2b6da..dfcff6d 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -21,9 +21,9 @@ #include <arch/acpi.h>
#if !CONFIG_DYNAMIC_CBMEM -void get_cbmem_table(uint64_t *base, uint64_t *size) +void get_cbmem_table(u64 *base, u64 *size) { - uint64_t top_of_ram = get_top_of_ram(); + u64 top_of_ram = get_top_of_ram();
if (top_of_ram >= HIGH_MEMORY_SIZE) { *base = top_of_ram - HIGH_MEMORY_SIZE; @@ -35,7 +35,7 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) }
#if !defined(__PRE_RAM__) -void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) +void __attribute__((weak)) backup_top_of_ram(u64 ramtop) { /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ } @@ -44,7 +44,7 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) * must implement get_top_of_ram() for both romstage and ramstage to support * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. */ -void set_top_of_ram(uint64_t ramtop) +void set_top_of_ram(u64 ramtop) { backup_top_of_ram(ramtop); cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); diff --git a/src/arch/x86/boot/pirq_routing.c b/src/arch/x86/boot/pirq_routing.c index 7fe20b2..f6f5f3f 100644 --- a/src/arch/x86/boot/pirq_routing.c +++ b/src/arch/x86/boot/pirq_routing.c @@ -25,8 +25,8 @@ #if CONFIG_DEBUG_PIRQ static void check_pirq_routing_table(struct irq_routing_table *rt) { - uint8_t *addr = (uint8_t *)rt; - uint8_t sum=0; + u8 *addr = (u8 *)rt; + u8 sum=0; int i;
printk(BIOS_INFO, "Checking Interrupt Routing Table consistency...\n"); @@ -79,10 +79,10 @@ static void check_pirq_routing_table(struct irq_routing_table *rt) static int verify_copy_pirq_routing_table(unsigned long addr, const struct irq_routing_table *routing_table) { int i; - uint8_t *rt_orig, *rt_curr; + u8 *rt_orig, *rt_curr;
- rt_curr = (uint8_t*)addr; - rt_orig = (uint8_t*)routing_table; + rt_curr = (u8*)addr; + rt_orig = (u8*)routing_table; printk(BIOS_INFO, "Verifying copy of Interrupt Routing Table at 0x%08lx... ", addr); for (i = 0; i < routing_table->size; i++) { if (*(rt_curr + i) != *(rt_orig + i)) { diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index 86b5cb0..5f1f708 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -11,9 +11,9 @@ #include <smp/spinlock.h>
/* Standard macro to see if a specific flag is changeable */ -static inline int flag_is_changeable_p(uint32_t flag) +static inline int flag_is_changeable_p(u32 flag) { - uint32_t f1, f2; + u32 f1, f2;
asm( "pushfl\n\t" diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index f64b2e7..5fdded0 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -16,7 +16,7 @@ enum regnames { NUM_REGS /* Number of registers. */ };
-static uint32_t gdb_stub_registers[NUM_REGS]; +static u32 gdb_stub_registers[NUM_REGS];
#define GDB_SIG0 0 /* Signal 0 */ #define GDB_SIGHUP 1 /* Hangup */ @@ -376,7 +376,7 @@ void x86_exception(struct eregs *info) { #if CONFIG_GDB_STUB int signo; - memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t)); + memcpy(gdb_stub_registers, info, 8*sizeof(u32)); gdb_stub_registers[PC] = info->eip; gdb_stub_registers[CS] = info->cs; gdb_stub_registers[PS] = info->eflags; @@ -412,7 +412,7 @@ void x86_exception(struct eregs *info) break; case 'G': /* set the value of the CPU registers - return OK */ copy_from_hex(&gdb_stub_registers, in_buffer + 1, sizeof(gdb_stub_registers)); - memcpy(info, gdb_stub_registers, 8*sizeof(uint32_t)); + memcpy(info, gdb_stub_registers, 8*sizeof(u32)); info->eip = gdb_stub_registers[PC]; info->cs = gdb_stub_registers[CS]; info->eflags = gdb_stub_registers[PS]; diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c index 7c8129a..bd02bf0 100644 --- a/src/arch/x86/lib/memset.c +++ b/src/arch/x86/lib/memset.c @@ -26,7 +26,7 @@ #include <string.h> #include <stdint.h>
-typedef uint32_t op_t; +typedef u32 op_t;
void *memset(void *dstpp, int c, size_t len) { diff --git a/src/arch/x86/lib/pci_ops_conf1.c b/src/arch/x86/lib/pci_ops_conf1.c index 77df4b3..b6eea24 100644 --- a/src/arch/x86/lib/pci_ops_conf1.c +++ b/src/arch/x86/lib/pci_ops_conf1.c @@ -17,21 +17,21 @@ ((where & 0xf00)<<16)) #endif
-static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, +static u8 pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, int where) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); return inb(0xCFC + (where & 3)); }
-static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, +static u16 pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, int where) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); return inw(0xCFC + (where & 2)); }
-static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, +static u32 pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, int where) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); @@ -39,21 +39,21 @@ static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, }
static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) + int where, u8 value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outb(value, 0xCFC + (where & 3)); }
static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) + int where, u16 value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outw(value, 0xCFC + (where & 2)); }
static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) + int where, u32 value) { outl(CONFIG_CMD(bus, devfn, where), 0xCF8); outl(value, 0xCFC); diff --git a/src/arch/x86/lib/pci_ops_mmconf.c b/src/arch/x86/lib/pci_ops_mmconf.c index 4eaf297..6d8826c 100644 --- a/src/arch/x86/lib/pci_ops_mmconf.c +++ b/src/arch/x86/lib/pci_ops_mmconf.c @@ -15,38 +15,38 @@ (((DEVFN) & 0xFF) << 12) |\ ((WHERE) & 0xFFF))
-static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, +static u8 pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, int where) { return (read8(PCI_MMIO_ADDR(bus, devfn, where))); }
-static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, +static u16 pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, int where) { return (read16(PCI_MMIO_ADDR(bus, devfn, where) & ~1)); }
-static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, +static u32 pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, int where) { return (read32(PCI_MMIO_ADDR(bus, devfn, where) & ~3)); }
static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) + int where, u8 value) { write8(PCI_MMIO_ADDR(bus, devfn, where), value); }
static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) + int where, u16 value) { write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value); }
static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) + int where, u32 value) { write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value); } diff --git a/src/arch/x86/lib/rom_media.c b/src/arch/x86/lib/rom_media.c index ed2122c..dcf610f 100644 --- a/src/arch/x86/lib/rom_media.c +++ b/src/arch/x86/lib/rom_media.c @@ -41,10 +41,10 @@ static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t count) // mapped location. To workaround that, we handle >0xf0000000 as real // memory pointer.
- if ((uint32_t)offset > (uint32_t)0xf0000000) + if ((u32)offset > (u32)0xf0000000) ptr = (void*)offset; else - ptr = (void*)(0 - (uint32_t)media->context + offset); + ptr = (void*)(0 - (u32)media->context + offset); return ptr; }
@@ -71,7 +71,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) { // Since the CBFS core always use ROM offset, we need to figure out // header->romsize even before media is initialized. struct cbfs_header *header = (struct cbfs_header*) - *(uint32_t*)(0xfffffffc); + *(u32*)(0xfffffffc); if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { #if defined(CONFIG_ROM_SIZE) printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); @@ -80,7 +80,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) { return -1; #endif } else { - uint32_t romsize = ntohl(header->romsize); + u32 romsize = ntohl(header->romsize); media->context = (void*)romsize; #if defined(CONFIG_ROM_SIZE) if (CONFIG_ROM_SIZE != romsize) diff --git a/src/arch/x86/lib/thread.c b/src/arch/x86/lib/thread.c index b1549b5..dc7b51d 100644 --- a/src/arch/x86/lib/thread.c +++ b/src/arch/x86/lib/thread.c @@ -21,14 +21,14 @@
/* The stack frame looks like the following after a pushad instruction. */ struct pushad_regs { - uint32_t edi; /* Offset 0x00 */ - uint32_t esi; /* Offset 0x04 */ - uint32_t ebp; /* Offset 0x08 */ - uint32_t esp; /* Offset 0x0c */ - uint32_t ebx; /* Offset 0x10 */ - uint32_t edx; /* Offset 0x14 */ - uint32_t ecx; /* Offset 0x18 */ - uint32_t eax; /* Offset 0x1c */ + u32 edi; /* Offset 0x00 */ + u32 esi; /* Offset 0x04 */ + u32 ebp; /* Offset 0x08 */ + u32 esp; /* Offset 0x0c */ + u32 ebx; /* Offset 0x10 */ + u32 edx; /* Offset 0x14 */ + u32 ecx; /* Offset 0x18 */ + u32 eax; /* Offset 0x1c */ };
static inline uintptr_t push_stack(uintptr_t cur_stack, uintptr_t value) diff --git a/src/console/post.c b/src/console/post.c index 4f2a87c..0d77653 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -33,7 +33,7 @@ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ -void __attribute__((weak)) mainboard_post(uint8_t value) +void __attribute__((weak)) mainboard_post(u8 value) { }
@@ -146,7 +146,7 @@ static void cmos_post_code(u8 value) } #endif /* CONFIG_CMOS_POST */
-void post_code(uint8_t value) +void post_code(u8 value) { #if !CONFIG_NO_POST #if CONFIG_CONSOLE_POST diff --git a/src/cpu/allwinner/a10/bootblock.c b/src/cpu/allwinner/a10/bootblock.c index 808982c..a1da155 100644 --- a/src/cpu/allwinner/a10/bootblock.c +++ b/src/cpu/allwinner/a10/bootblock.c @@ -12,7 +12,7 @@
void bootblock_soc_init(void) { - uint32_t sctlr; + u32 sctlr;
/* enable dcache */ sctlr = read_sctlr(); diff --git a/src/cpu/allwinner/a10/twi.c b/src/cpu/allwinner/a10/twi.c index d6a0127..2625f2d 100644 --- a/src/cpu/allwinner/a10/twi.c +++ b/src/cpu/allwinner/a10/twi.c @@ -110,7 +110,7 @@ static void i2c_send_stop(struct a1x_twi *twi) }
static int i2c_read(unsigned bus, unsigned chip, unsigned addr, - uint8_t *buf, unsigned len) + u8 *buf, unsigned len) { unsigned count = len; enum twi_status expected_status; @@ -170,7 +170,7 @@ static int i2c_read(unsigned bus, unsigned chip, unsigned addr, }
static int i2c_write(unsigned bus, unsigned chip, unsigned addr, - const uint8_t *buf, unsigned len) + const u8 *buf, unsigned len) { unsigned count = len; struct a1x_twi *twi = (void *)TWI_BASE(bus); diff --git a/src/cpu/amd/agesa/family15rl/udelay.c b/src/cpu/amd/agesa/family15rl/udelay.c index 5873237..9c4b145 100644 --- a/src/cpu/amd/agesa/family15rl/udelay.c +++ b/src/cpu/amd/agesa/family15rl/udelay.c @@ -12,12 +12,12 @@ #include <delay.h> #include <stdint.h>
-void udelay(uint32_t us) +void udelay(u32 us) { - uint8_t fid, did, pstate_idx; - uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks; + u8 fid, did, pstate_idx; + u64 tsc_clock, tsc_start, tsc_now, tsc_wait_ticks; msr_t msr; - const uint64_t tsc_base = 100000000; + const u64 tsc_base = 100000000;
/* Get initial timestamp before we do the math */ tsc_start = rdtscll(); diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c index 5873237..9c4b145 100644 --- a/src/cpu/amd/agesa/family15tn/udelay.c +++ b/src/cpu/amd/agesa/family15tn/udelay.c @@ -12,12 +12,12 @@ #include <delay.h> #include <stdint.h>
-void udelay(uint32_t us) +void udelay(u32 us) { - uint8_t fid, did, pstate_idx; - uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks; + u8 fid, did, pstate_idx; + u64 tsc_clock, tsc_start, tsc_now, tsc_wait_ticks; msr_t msr; - const uint64_t tsc_base = 100000000; + const u64 tsc_base = 100000000;
/* Get initial timestamp before we do the math */ tsc_start = rdtscll(); diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index d9942de..501266f 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -43,7 +43,7 @@ static void enable_apic_ext_id(int nodes)
//enable APIC_EXIT_ID all the nodes for(nodeid=0; nodeid<nodes; nodeid++){ - uint32_t val; + u32 val; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); val = pci_read_config32(dev, 0x68); val |= (1<<17)|(1<<18); diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index a545762..59054c3 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -8,14 +8,14 @@
static inline unsigned get_core_num_in_bsp(unsigned nodeid) { - uint32_t dword; + u32 dword; dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0xe8); dword >>= 12; dword &= 3; return dword; }
-static inline uint8_t set_apicid_cpuid_lo(void) +static inline u8 set_apicid_cpuid_lo(void) { #if !CONFIG_K8_REV_F_SUPPORT if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set @@ -32,7 +32,7 @@ static inline uint8_t set_apicid_cpuid_lo(void)
static inline void real_start_other_core(unsigned nodeid) { - uint32_t dword; + u32 dword; // set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44); dword |= 1<<27; // NbMcaToMstCpuEn bit diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 260e83e..4a746f0 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -44,8 +44,8 @@ void cpus_ready_for_init(void) #if !CONFIG_K8_REV_F_SUPPORT int is_e0_later_in_bsp(int nodeid) { - uint32_t val; - uint32_t val_old; + u32 val; + u32 val_old; int e0_later; if (nodeid == 0) { // we don't need to do that for node 0 in core0/node0 return !is_cpu_pre_e0(); @@ -72,7 +72,7 @@ int is_e0_later_in_bsp(int nodeid) #if CONFIG_K8_REV_F_SUPPORT int is_cpu_f0_in_bsp(int nodeid) { - uint32_t dword; + u32 dword; device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 3)); dword = pci_read_config32(dev, 0xfc); @@ -218,7 +218,7 @@ static inline void clear_2M_ram(unsigned long basek, }
/* clear memory 2M (limitk - basek) */ - addr = (void *)(((uint32_t) addr) | ((basek & 0x7ff) << 10)); + addr = (void *)(((u32) addr) | ((basek & 0x7ff) << 10)); memset(addr, 0, size); }
@@ -230,7 +230,7 @@ static void init_ecc_memory(unsigned node_id)
device_t f1_dev, f2_dev, f3_dev; int enable_scrubbing; - uint32_t dcl; + u32 dcl;
f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1)); if (!f1_dev) { @@ -282,7 +282,7 @@ static void init_ecc_memory(unsigned node_id) if (!is_cpu_pre_e0()) { #endif
- uint32_t val; + u32 val; val = pci_read_config32(f1_dev, 0xf0); if (val & 1) { hole_startk = ((val & (0xff << 24)) >> 10); diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c index 4a53fea..fa12cba 100644 --- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c +++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <cpu/amd/microcode.h>
-static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = { +static u8 microcode_updates[] __attribute__ ((aligned(16))) = {
#if !CONFIG_K8_REV_F_SUPPORT #include "microcode_rev_c.h" diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 2ef99fe..0e35122 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -372,22 +372,22 @@ write_pstates: #else
-static uint8_t vid_to_reg(uint32_t vid) +static u8 vid_to_reg(u32 vid) { return (1550 - vid) / 25; }
-static uint32_t vid_from_reg(uint8_t val) +static u32 vid_from_reg(u8 val) { return (val == 0x1f ? 0 : 1550 - val * 25); }
-static uint8_t freq_to_fid(uint32_t freq) +static u8 freq_to_fid(u32 freq) { return (freq - 800) / 100; } /* Return a frequency in MHz, given an input fid */ -static uint32_t fid_to_freq(uint32_t fid) +static u32 fid_to_freq(u32 fid) { return 800 + (fid * 100); } @@ -395,18 +395,18 @@ static uint32_t fid_to_freq(uint32_t fid) #define MAXP 7
struct pstate { - uint16_t freqMhz; /* in MHz */ - uint16_t voltage; /* in mV */ - uint16_t tdp; /* in W * 10 */ + u16 freqMhz; /* in MHz */ + u16 voltage; /* in mV */ + u16 tdp; /* in W * 10 */ };
struct cpuentry { - uint16_t modelnr; /* numeric model value, unused in code */ - uint8_t brandID; /* CPUID 8000_0001h EBX [11:6] (BrandID) */ - uint32_t cpuid; /* CPUID 8000_0001h EAX [31:0] (CPUID) */ - uint8_t maxFID; /* FID/VID Status MaxFID Field */ - uint8_t startFID; /* FID/VID Status StartFID Field */ - uint16_t pwr:12; /* Thermal Design Power of Max P-State *10 (fixed point) */ + u16 modelnr; /* numeric model value, unused in code */ + u8 brandID; /* CPUID 8000_0001h EBX [11:6] (BrandID) */ + u32 cpuid; /* CPUID 8000_0001h EAX [31:0] (CPUID) */ + u8 maxFID; /* FID/VID Status MaxFID Field */ + u8 startFID; /* FID/VID Status StartFID Field */ + u16 pwr:12; /* Thermal Design Power of Max P-State *10 (fixed point) */ /* Other MAX P state are read from CPU, other P states in following table */ struct pstate pstates[MAXP]; }; @@ -752,7 +752,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
u8 cmp_cap; struct cpuentry *data = NULL; - uint32_t control; + u32 control; int i = 0, index = 0, Pstate_num = 0, dev = 0; msr_t msr; u8 Pstate_fid[MAXP+1]; diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 033ec53..441c725 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -7,15 +7,15 @@ #include <cpu/x86/cache.h>
/* These will likely move to some device node or cbmem. */ -static uint64_t amd_topmem = 0; -static uint64_t amd_topmem2 = 0; +static u64 amd_topmem = 0; +static u64 amd_topmem2 = 0;
-uint64_t bsp_topmem(void) +u64 bsp_topmem(void) { return amd_topmem; }
-uint64_t bsp_topmem2(void) +u64 bsp_topmem2(void) { return amd_topmem2; } @@ -40,26 +40,26 @@ void setup_bsp_ramtop(void) "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", __func__, msr2.lo, msr2.hi);
- amd_topmem = (uint64_t) msr.hi<<32 | msr.lo; - amd_topmem2 = (uint64_t) msr2.hi<<32 | msr2.lo; + amd_topmem = (u64) msr.hi<<32 | msr.lo; + amd_topmem2 = (u64) msr2.hi<<32 | msr2.lo; }
static void setup_ap_ramtop(void) { msr_t msr; - uint64_t v; + u64 v;
v = bsp_topmem(); if (!v) return;
msr.hi = v >> 32; - msr.lo = (uint32_t) v; + msr.lo = (u32) v; wrmsr(TOP_MEM, msr);
v = bsp_topmem2(); msr.hi = v >> 32; - msr.lo = (uint32_t) v; + msr.lo = (u32) v; wrmsr(TOP_MEM2, msr); }
@@ -94,7 +94,7 @@ void amd_setup_mtrrs(void)
/* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); - if (bsp_topmem2() > (uint64_t)1<<32) { + if (bsp_topmem2() > (u64)1<<32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; if(has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 62d25bd..ecfd3db 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -46,7 +46,7 @@ static void check_for_warm_reset(void) } }
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +static void set_var_mtrr(int reg, u32 base, u32 size, int type) { #ifndef CONFIG_CPU_ADDR_BITS #error "CONFIG_CPU_ADDR_BITS must be set." diff --git a/src/cpu/intel/haswell/monotonic_timer.c b/src/cpu/intel/haswell/monotonic_timer.c index c51bcbd..0ab8eb4 100644 --- a/src/cpu/intel/haswell/monotonic_timer.c +++ b/src/cpu/intel/haswell/monotonic_timer.c @@ -24,10 +24,10 @@ static struct monotonic_counter { int initialized; struct mono_time time; - uint32_t last_value; + u32 last_value; } mono_counter;
-static inline uint32_t read_counter_msr(void) +static inline u32 read_counter_msr(void) { /* Even though the MSR is 64-bit it is assumed that the hardware * is polled frequently enough to only use the lower 32-bits. */ @@ -40,8 +40,8 @@ static inline uint32_t read_counter_msr(void)
void timer_monotonic_get(struct mono_time *mt) { - uint32_t current_tick; - uint32_t usecs_elapsed; + u32 current_tick; + u32 usecs_elapsed;
if (!mono_counter.initialized) { mono_counter.last_value = read_counter_msr(); diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 8a2bff1..07c75a8 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -84,7 +84,7 @@ static int get_fsb(void)
static void gen_pstate_entries(const sst_table_t *const pstates, const int cpuID, const int cores_per_package, - const uint8_t coordination) + const u8 coordination) { int i; int frequency; @@ -142,7 +142,7 @@ void generate_cpu_entries(void) int num_cstates; acpi_cstate_t *cstates; sst_table_t pstates; - uint8_t coordination; + u8 coordination;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index f2cff04..7cb15df 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -36,8 +36,8 @@ static void speedstep_get_limits(sst_params_t *const params) { msr_t msr;
- const uint16_t cpu_id = (cpuid_eax(1) >> 4) & 0xffff; - const uint32_t state_mask = + const u16 cpu_id = (cpuid_eax(1) >> 4) & 0xffff; + const u32 state_mask = /* Penryn supports non integer (i.e. half) ratios. */ ((cpu_id == 0x1067) ? SPEEDSTEP_RATIO_NONINT : 0) | SPEEDSTEP_RATIO_VALUE_MASK | SPEEDSTEP_VID_MASK; diff --git a/src/cpu/ti/am335x/bootblock.c b/src/cpu/ti/am335x/bootblock.c index f586e17..9ac16f7 100644 --- a/src/cpu/ti/am335x/bootblock.c +++ b/src/cpu/ti/am335x/bootblock.c @@ -24,7 +24,7 @@
void bootblock_soc_init(void) { - uint32_t sctlr; + u32 sctlr;
/* enable dcache */ sctlr = read_sctlr(); diff --git a/src/cpu/ti/am335x/dmtimer.c b/src/cpu/ti/am335x/dmtimer.c index 6a55d9d..023688c 100644 --- a/src/cpu/ti/am335x/dmtimer.c +++ b/src/cpu/ti/am335x/dmtimer.c @@ -23,7 +23,7 @@ void dmtimer_start(int num) { }
-uint64_t dmtimer_raw_value(int num) +u64 dmtimer_raw_value(int num) { return 0; } diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index 5ed943e..865e78f 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -35,7 +35,7 @@ struct config_headers { struct omap_image_headers { union { struct config_headers config_headers; - uint8_t bytes[512]; + u8 bytes[512]; }; struct gp_device_header image_header; }; diff --git a/src/cpu/ti/am335x/monotonic_timer.c b/src/cpu/ti/am335x/monotonic_timer.c index 9a9083c..b077348 100644 --- a/src/cpu/ti/am335x/monotonic_timer.c +++ b/src/cpu/ti/am335x/monotonic_timer.c @@ -26,15 +26,15 @@ static struct monotonic_counter { int initialized; struct mono_time time; - uint64_t last_value; + u64 last_value; } mono_counter;
-static const uint32_t clocks_per_usec = OSC_HZ/1000000; +static const u32 clocks_per_usec = OSC_HZ/1000000;
void timer_monotonic_get(struct mono_time *mt) { - uint64_t current_tick; - uint64_t usecs_elapsed; + u64 current_tick; + u64 usecs_elapsed;
if (!mono_counter.initialized) { init_timer(); diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 5756834..6bb1c78 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -37,9 +37,9 @@ * Initialise the serial port with the given baudrate divisor. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void am335x_uart_init(struct am335x_uart *uart, uint16_t div) +static void am335x_uart_init(struct am335x_uart *uart, u16 div) { - uint16_t lcr_orig, efr_orig, mcr_orig; + u16 lcr_orig, efr_orig, mcr_orig;
/* reset the UART */ write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc); @@ -167,7 +167,7 @@ uintptr_t uart_platform_base(int idx) void uart_init(int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); - uint16_t div = (uint16_t) uart_baudrate_divisor( + u16 div = (u16) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); } diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index a113143..b39ee21 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -129,14 +129,14 @@ void udelay(u32 usecs) static struct monotonic_counter { int initialized; struct mono_time time; - uint32_t last_value; + u32 last_value; } mono_counter;
void timer_monotonic_get(struct mono_time *mt) { - uint32_t current_tick; - uint32_t usecs_elapsed; - uint32_t timer_fsb; + u32 current_tick; + u32 usecs_elapsed; + u32 timer_fsb;
if (!mono_counter.initialized) { init_timer(); diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3e293f6..b2e6a23 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -44,25 +44,25 @@ #define MAX_APIC_IDS 256 /* This needs to match the layout in the .module_parametrs section. */ struct sipi_params { - uint16_t gdtlimit; - uint32_t gdt; - uint16_t unused; - uint32_t idt_ptr; - uint32_t stack_top; - uint32_t stack_size; - uint32_t microcode_lock; /* 0xffffffff means parallel loading. */ - uint32_t microcode_ptr; - uint32_t msr_table_ptr; - uint32_t msr_count; - uint32_t c_handler; + u16 gdtlimit; + u32 gdt; + u16 unused; + u32 idt_ptr; + u32 stack_top; + u32 stack_size; + u32 microcode_lock; /* 0xffffffff means parallel loading. */ + u32 microcode_ptr; + u32 msr_table_ptr; + u32 msr_count; + u32 c_handler; atomic_t ap_count; } __attribute__((packed));
/* This also needs to match the assembly code for saved MSR encoding. */ struct saved_msr { - uint32_t index; - uint32_t lo; - uint32_t hi; + u32 index; + u32 lo; + u32 hi; } __attribute__((packed));
@@ -72,7 +72,7 @@ extern char _binary_sipi_vector_start[]; /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const u32 sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE;
struct mp_flight_plan { @@ -168,11 +168,11 @@ static void asmlinkage ap_init(unsigned int cpu)
static void setup_default_sipi_vector_params(struct sipi_params *sp) { - sp->gdt = (uint32_t)&gdt; - sp->gdtlimit = (uint32_t)&gdt_end - (u32)&gdt - 1; - sp->idt_ptr = (uint32_t)&idtarg; + sp->gdt = (u32)&gdt; + sp->gdtlimit = (u32)&gdt_end - (u32)&gdt - 1; + sp->idt_ptr = (u32)&idtarg; sp->stack_size = CONFIG_STACK_SIZE; - sp->stack_top = (uint32_t)&_estack; + sp->stack_top = (u32)&_estack; /* Adjust the stack top to take into account cpu_info. */ sp->stack_top -= sizeof(struct cpu_info); } @@ -292,17 +292,17 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params)
setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (u32)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (u32)mp_params->microcode_pointer; /* Pass on abiility to load microcode in parallel. */ if (mp_params->parallel_microcode_load) { sp->microcode_lock = 0; } else { sp->microcode_lock = ~0; } - sp->c_handler = (uint32_t)&ap_init; + sp->c_handler = (u32)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0);
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 69cd2d2..be0068e 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -153,12 +153,12 @@ static inline unsigned int fls(unsigned int x) /* If the default type is UC use the hole carving algorithm for a range. */ #define MTRR_RANGE_UC_USE_HOLE (1 << MTRR_ALGO_SHIFT)
-static inline uint32_t range_entry_base_mtrr_addr(struct range_entry *r) +static inline u32 range_entry_base_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_base(r)); }
-static inline uint32_t range_entry_end_mtrr_addr(struct range_entry *r) +static inline u32 range_entry_end_mtrr_addr(struct range_entry *r) { return PHYS_TO_RANGE_ADDR(range_entry_end(r)); } @@ -237,15 +237,15 @@ static struct memranges *get_physical_address_space(void) * It also describes the offset in byte intervals to store the calculated MTRR * type in an array. */ struct fixed_mtrr_desc { - uint32_t begin; - uint32_t end; - uint32_t step; + u32 begin; + u32 end; + u32 step; int range_index; int msr_index_base; };
/* Shared MTRR calculations. Can be reused by APs. */ -static uint8_t fixed_mtrr_types[NUM_FIXED_RANGES]; +static u8 fixed_mtrr_types[NUM_FIXED_RANGES];
/* Fixed MTRR descriptors. */ static const struct fixed_mtrr_desc fixed_mtrr_desc[] = { @@ -264,8 +264,8 @@ static void calc_fixed_mtrrs(void) struct range_entry *r; const struct fixed_mtrr_desc *desc; const struct fixed_mtrr_desc *last_desc; - uint32_t begin; - uint32_t end; + u32 begin; + u32 end; int type_index;
if (fixed_mtrr_types_initialized) @@ -416,7 +416,7 @@ static void clear_var_mtrr(int index) }
static void prep_var_mtrr(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + u32 base, u32 size, int mtrr_type) { struct var_mtrr_regs *regs; resource_t rbase; @@ -458,12 +458,12 @@ static void prep_var_mtrr(struct var_mtrr_state *var_state, }
static void calc_var_mtrr_range(struct var_mtrr_state *var_state, - uint32_t base, uint32_t size, int mtrr_type) + u32 base, u32 size, int mtrr_type) { while (size != 0) { - uint32_t addr_lsb; - uint32_t size_msb; - uint32_t mtrr_size; + u32 addr_lsb; + u32 size_msb; + u32 mtrr_size;
addr_lsb = fls(base); size_msb = fms(size); @@ -488,7 +488,7 @@ static void calc_var_mtrr_range(struct var_mtrr_state *var_state, static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, struct range_entry *r) { - uint32_t a1, a2, b1, b2; + u32 a1, a2, b1, b2; int mtrr_type; struct range_entry *next;
@@ -535,7 +535,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, * entry. If so perform an optimization of covering a larger range * defined by the base address' alignment. */ if (a1 >= RANGE_4GB && next == NULL) { - uint32_t addr_lsb; + u32 addr_lsb;
addr_lsb = fls(a1); b2 = (1 << addr_lsb) + a1; @@ -566,7 +566,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, static void calc_var_mtrrs_without_hole(struct var_mtrr_state *var_state, struct range_entry *r) { - uint32_t a1, a2, b1, b2, c1, c2; + u32 a1, a2, b1, b2, c1, c2; int mtrr_type;
/* diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 9be415d..cb7f9ca 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -46,8 +46,8 @@ static void paging_on(void *pdp) void *map_2M_page(unsigned long page) { struct pde { - uint32_t addr_lo; - uint32_t addr_hi; + u32 addr_lo; + u32 addr_hi; } __attribute__ ((packed)); struct pg_table { struct pde pd[2048]; @@ -73,10 +73,10 @@ void *map_2M_page(unsigned long page) memset(&pgtbl[index].pdp, 0, sizeof(pgtbl[index].pdp)); pd = pgtbl[index].pd; pdp = pgtbl[index].pdp; - pdp[0].addr_lo = ((uint32_t)&pd[512*0])|1; - pdp[1].addr_lo = ((uint32_t)&pd[512*1])|1; - pdp[2].addr_lo = ((uint32_t)&pd[512*2])|1; - pdp[3].addr_lo = ((uint32_t)&pd[512*3])|1; + pdp[0].addr_lo = ((u32)&pd[512*0])|1; + pdp[1].addr_lo = ((u32)&pd[512*1])|1; + pdp[2].addr_lo = ((u32)&pd[512*2])|1; + pdp[3].addr_lo = ((u32)&pd[512*3])|1; /* The first half of the page table is identity mapped */ for(i = 0; i < 1024; i++) { pd[i].addr_lo = ((i & 0x3ff) << 21)| 0xE3; diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 478ae8c..c57aba5 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -63,7 +63,7 @@ extern unsigned char _binary_smm_start[]; */ struct smm_entry_ins { char jmp_rel; - uint16_t rel16; + u16 rel16; } __attribute__ ((packed));
/* @@ -87,9 +87,9 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, * the jmp instruction needs to be taken into account. */ cur = entry_start; for (i = 0; i < num; i++) { - uint32_t disp = (uint32_t)jmp_target; + u32 disp = (u32)jmp_target;
- disp -= sizeof(entry) + (uint32_t)cur; + disp -= sizeof(entry) + (u32)cur; printk(BIOS_DEBUG, "SMM Module: placing jmp sequence at %p rel16 0x%04x\n", cur, disp); diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 07a4053..df6f9db 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -196,13 +196,13 @@ void udelay(unsigned us) static struct monotonic_counter { int initialized; struct mono_time time; - uint64_t last_value; + u64 last_value; } mono_counter;
void timer_monotonic_get(struct mono_time *mt) { - uint64_t current_tick; - uint64_t ticks_elapsed; + u64 current_tick; + u64 ticks_elapsed;
if (!mono_counter.initialized) { init_timer(); @@ -215,7 +215,7 @@ void timer_monotonic_get(struct mono_time *mt)
/* Update current time and tick values only if a full tick occurred. */ if (ticks_elapsed >= clocks_per_usec) { - uint64_t usecs_elapsed; + u64 usecs_elapsed;
usecs_elapsed = ticks_elapsed / clocks_per_usec; mono_time_add_usecs(&mono_counter.time, (long)usecs_elapsed); diff --git a/src/device/device.c b/src/device/device.c index e068cee..b907cfd 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -98,8 +98,8 @@ DECLARE_SPIN_LOCK(dev_lock)
#if CONFIG_GFXUMA /* IGD UMA memory */ -uint64_t uma_memory_base = 0; -uint64_t uma_memory_size = 0; +u64 uma_memory_base = 0; +u64 uma_memory_size = 0; #endif
/** diff --git a/src/device/oprom/yabel/device.c b/src/device/oprom/yabel/device.c index 2f41847..527c51a 100644 --- a/src/device/oprom/yabel/device.c +++ b/src/device/oprom/yabel/device.c @@ -136,7 +136,7 @@ void biosemu_dev_get_addr_info(void) { // get bus/dev/fn from assigned-addresses - int32_t len; + s32 len; //max. 6 BARs and 1 Exp.ROM plus CfgSpace and 3 legacy ranges assigned_address_t buf[11]; len = diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 8351e9c..2096858 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1330,10 +1330,10 @@ static int swizzle_irq_pins(device_t dev, device_t *parent_bridge) { device_t parent; /* Our current device's parent device */ device_t child; /* The child device of the parent */ - uint8_t parent_bus = 0; /* Parent Bus number */ - uint16_t parent_devfn = 0; /* Parent Device and Function number */ - uint16_t child_devfn = 0; /* Child Device and Function number */ - uint8_t swizzled_pin = 0; /* Pin swizzled across a bridge */ + u8 parent_bus = 0; /* Parent Bus number */ + u16 parent_devfn = 0; /* Parent Device and Function number */ + u16 child_devfn = 0; /* Child Device and Function number */ + u8 swizzled_pin = 0; /* Pin swizzled across a bridge */
/* Start with PIN A = 0 ... D = 3 */ swizzled_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN) - 1; @@ -1396,10 +1396,10 @@ static int swizzle_irq_pins(device_t dev, device_t *parent_bridge) */ int get_pci_irq_pins(device_t dev, device_t *parent_bdg) { - uint8_t bus = 0; /* The bus this device is on */ - uint16_t devfn = 0; /* This device's device and function numbers */ - uint8_t int_pin = 0; /* Interrupt pin used by the device */ - uint8_t target_pin = 0; /* Interrupt pin we want to assign an IRQ to */ + u8 bus = 0; /* The bus this device is on */ + u16 devfn = 0; /* This device's device and function numbers */ + u8 int_pin = 0; /* Interrupt pin used by the device */ + u8 target_pin = 0; /* Interrupt pin we want to assign an IRQ to */
/* Make sure this device is enabled */ if (!(dev->enabled && (dev->path.type == DEVICE_PATH_PCI))) diff --git a/src/drivers/ams/as3722rtc.c b/src/drivers/ams/as3722rtc.c index 8fe5748..9d8060d 100644 --- a/src/drivers/ams/as3722rtc.c +++ b/src/drivers/ams/as3722rtc.c @@ -38,15 +38,15 @@ enum { AS3722_RTC_CONTROL_ON = 0x1 << 2 };
-static uint8_t as3722_read(enum AS3722_RTC_REG reg) +static u8 as3722_read(enum AS3722_RTC_REG reg) { - uint8_t val; + u8 val; i2c_readb(CONFIG_DRIVERS_AS3722_RTC_BUS, CONFIG_DRIVERS_AS3722_RTC_ADDR, reg, &val); return val; }
-static void as3722_write(enum AS3722_RTC_REG reg, uint8_t val) +static void as3722_write(enum AS3722_RTC_REG reg, u8 val) { i2c_writeb(CONFIG_DRIVERS_AS3722_RTC_BUS, CONFIG_DRIVERS_AS3722_RTC_ADDR, reg, val); @@ -58,7 +58,7 @@ static void as3722rtc_init(void) if (initialized) return;
- uint8_t control = as3722_read(AS3722_RTC_CONTROL); + u8 control = as3722_read(AS3722_RTC_CONTROL); as3722_write(AS3722_RTC_CONTROL, control | AS3722_RTC_CONTROL_ON);
initialized = 1; diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 1c659eb..755d1c5 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -201,7 +201,7 @@ enum
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) static void -write_hidden_dac (uint8_t data) +write_hidden_dac (u8 data) { inb (0x3c8); inb (0x3c6); @@ -215,12 +215,12 @@ write_hidden_dac (uint8_t data) static void cirrus_init(struct device *dev) { #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - uint8_t cr_ext, cr_overlay; + u8 cr_ext, cr_overlay; unsigned pitch = (width * 4) / VGA_CR_PITCH_DIVISOR; - uint8_t sr_ext = 0, hidden_dac = 0; + u8 sr_ext = 0, hidden_dac = 0; unsigned vdisplay_end = height - 2; unsigned line_compare = 0x3ff; - uint8_t overflow, cell_height_reg; + u8 overflow, cell_height_reg; unsigned horizontal_end = width / VGA_CR_WIDTH_DIVISOR; unsigned horizontal_total = horizontal_end + 40; unsigned horizontal_blank_start = horizontal_end; diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 49bcdd7..914d991 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -85,10 +85,10 @@ int tis_init(void) return 0; }
-static ssize_t tpm_transmit(const uint8_t *buf, size_t bufsiz) +static ssize_t tpm_transmit(const u8 *buf, size_t bufsiz) { int rc; - uint32_t count, ordinal; + u32 count, ordinal;
struct tpm_chip *chip = &g_chip;
@@ -108,7 +108,7 @@ static ssize_t tpm_transmit(const uint8_t *buf, size_t bufsiz) }
ASSERT(chip->vendor.send); - rc = chip->vendor.send(chip, (uint8_t *) buf, count); + rc = chip->vendor.send(chip, (u8 *) buf, count); if (rc < 0) { printk(BIOS_DEBUG, "tpm_transmit: tpm_send error\n"); goto out; @@ -120,7 +120,7 @@ static ssize_t tpm_transmit(const uint8_t *buf, size_t bufsiz) int timeout = 2 * 60 * 1000; /* two minutes timeout */ while (timeout) { ASSERT(chip->vendor.status); - uint8_t status = chip->vendor.status(chip); + u8 status = chip->vendor.status(chip); if ((status & chip->vendor.req_complete_mask) == chip->vendor.req_complete_val) { goto out_recv; @@ -143,17 +143,17 @@ static ssize_t tpm_transmit(const uint8_t *buf, size_t bufsiz)
out_recv:
- rc = chip->vendor.recv(chip, (uint8_t *) buf, TPM_BUFSIZE); + rc = chip->vendor.recv(chip, (u8 *) buf, TPM_BUFSIZE); if (rc < 0) printk(BIOS_DEBUG, "tpm_transmit: tpm_recv: error %zd\n", rc); out: return rc; }
-int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, - uint8_t *recvbuf, size_t *rbuf_len) +int tis_sendrecv(const u8 *sendbuf, size_t sbuf_size, + u8 *recvbuf, size_t *rbuf_len) { - uint8_t buf[TPM_BUFSIZE]; + u8 buf[TPM_BUFSIZE];
if (sizeof(buf) < sbuf_size) return -1; diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 6f68789..33af50a 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -88,7 +88,7 @@ static const char * const chip_name[] = { struct tpm_inf_dev { unsigned bus; unsigned int addr; - uint8_t buf[TPM_BUFSIZE + sizeof(uint8_t)]; // max. buffer size + addr + u8 buf[TPM_BUFSIZE + sizeof(u8)]; // max. buffer size + addr enum i2c_chip_type chip_type; };
@@ -110,7 +110,7 @@ static struct tpm_inf_dev tpm_dev = { * * Return -1 on error, 0 on success. */ -static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) +static int iic_tpm_read(u8 addr, u8 *buffer, size_t len) { int rc; int count; @@ -170,9 +170,9 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len) return 0; }
-static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, +static int iic_tpm_write_generic(u8 addr, u8 *buffer, size_t len, unsigned int sleep_time, - uint8_t max_count) + u8 max_count) { int rc = 0; int count; @@ -221,7 +221,7 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len, * * Return -EIO on error, 0 on success */ -static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len) +static int iic_tpm_write(u8 addr, u8 *buffer, size_t len) { return iic_tpm_write_generic(addr, buffer, len, SLEEP_DURATION, MAX_COUNT); @@ -231,7 +231,7 @@ static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len) * This function is needed especially for the cleanup situation after * sending TPM_READY * */ -static int iic_tpm_write_long(uint8_t addr, uint8_t *buffer, size_t len) +static int iic_tpm_write_long(u8 addr, u8 *buffer, size_t len) { return iic_tpm_write_generic(addr, buffer, len, SLEEP_DURATION_LONG, MAX_COUNT_LONG); @@ -261,7 +261,7 @@ enum tis_status {
static int check_locality(struct tpm_chip *chip, int loc) { - uint8_t buf; + u8 buf;
if (iic_tpm_read(TPM_ACCESS(loc), &buf, 1) < 0) return -1; @@ -277,7 +277,7 @@ static int check_locality(struct tpm_chip *chip, int loc)
static void release_locality(struct tpm_chip *chip, int loc, int force) { - uint8_t buf; + u8 buf; if (iic_tpm_read(TPM_ACCESS(loc), &buf, 1) < 0) return;
@@ -290,7 +290,7 @@ static void release_locality(struct tpm_chip *chip, int loc, int force)
static int request_locality(struct tpm_chip *chip, int loc) { - uint8_t buf = TPM_ACCESS_REQUEST_USE; + u8 buf = TPM_ACCESS_REQUEST_USE;
if (check_locality(chip, loc) >= 0) return loc; /* we already have the locality */ @@ -309,10 +309,10 @@ static int request_locality(struct tpm_chip *chip, int loc) return -1; }
-static uint8_t tpm_tis_i2c_status(struct tpm_chip *chip) +static u8 tpm_tis_i2c_status(struct tpm_chip *chip) { /* NOTE: Since I2C read may fail, return 0 in this case --> time-out */ - uint8_t buf; + u8 buf; if (iic_tpm_read(TPM_STS(chip->vendor.locality), &buf, 1) < 0) return 0; else @@ -322,14 +322,14 @@ static uint8_t tpm_tis_i2c_status(struct tpm_chip *chip) static void tpm_tis_i2c_ready(struct tpm_chip *chip) { /* this causes the current command to be aborted */ - uint8_t buf = TPM_STS_COMMAND_READY; + u8 buf = TPM_STS_COMMAND_READY; iic_tpm_write_long(TPM_STS(chip->vendor.locality), &buf, 1); }
static ssize_t get_burstcount(struct tpm_chip *chip) { ssize_t burstcnt; - uint8_t buf[3]; + u8 buf[3];
/* wait for burstcount */ int timeout = 2 * 1000; /* 2s timeout */ @@ -348,7 +348,7 @@ static ssize_t get_burstcount(struct tpm_chip *chip) return -1; }
-static int wait_for_stat(struct tpm_chip *chip, uint8_t mask, int *status) +static int wait_for_stat(struct tpm_chip *chip, u8 mask, int *status) { unsigned long timeout = 2 * 1024; while (timeout) { @@ -362,7 +362,7 @@ static int wait_for_stat(struct tpm_chip *chip, uint8_t mask, int *status) return -1; }
-static int recv_data(struct tpm_chip *chip, uint8_t *buf, size_t count) +static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count) { size_t size = 0;
@@ -388,10 +388,10 @@ static int recv_data(struct tpm_chip *chip, uint8_t *buf, size_t count) return size; }
-static int tpm_tis_i2c_recv(struct tpm_chip *chip, uint8_t *buf, size_t count) +static int tpm_tis_i2c_recv(struct tpm_chip *chip, u8 *buf, size_t count) { int size = 0; - uint32_t expected; + u32 expected; int status;
if (count < TPM_HEADER_SIZE) { @@ -435,11 +435,11 @@ out: return size; }
-static int tpm_tis_i2c_send(struct tpm_chip *chip, uint8_t *buf, size_t len) +static int tpm_tis_i2c_send(struct tpm_chip *chip, u8 *buf, size_t len) { int status; size_t count = 0; - uint8_t sts = TPM_STS_GO; + u8 sts = TPM_STS_GO;
if (len > TPM_BUFSIZE) return -1; /* command is too long for our TPM, sorry */ @@ -505,9 +505,9 @@ static struct tpm_vendor_specific tpm_tis_i2c = {
/* Initialization of I2C TPM */
-int tpm_vendor_init(unsigned bus, uint32_t dev_addr) +int tpm_vendor_init(unsigned bus, u32 dev_addr) { - uint32_t vendor; + u32 vendor; unsigned int old_addr; struct tpm_chip *chip; extern struct tpm_chip g_chip; @@ -528,7 +528,7 @@ int tpm_vendor_init(unsigned bus, uint32_t dev_addr) goto out_err;
/* Read four bytes from DID_VID register */ - if (iic_tpm_read(TPM_DID_VID(0), (uint8_t *)&vendor, 4) < 0) + if (iic_tpm_read(TPM_DID_VID(0), (u8 *)&vendor, 4) < 0) goto out_release;
if (vendor == TPM_TIS_I2C_DID_VID_9645) { diff --git a/src/drivers/i2c/w83793/w83793.c b/src/drivers/i2c/w83793/w83793.c index 4b947d7..61ef4be 100644 --- a/src/drivers/i2c/w83793/w83793.c +++ b/src/drivers/i2c/w83793/w83793.c @@ -25,7 +25,7 @@ #include <device/smbus.h> #include "chip.h"
-static int w83793_fan_limit(struct device *dev, int fan, uint16_t limit) +static int w83793_fan_limit(struct device *dev, int fan, u16 limit) { return smbus_write_byte(dev, 0x90 + fan * 2, limit >> 8) || smbus_write_byte(dev, 0x91 + fan * 2, limit & 0xff); @@ -97,7 +97,7 @@ static int w83793_tr_fan_level(struct device *dev, int fan, const char *level) static void w83793_init(struct device *dev) { struct drivers_i2c_w83793_config *config = dev->chip_info; - uint16_t id; + u16 id; int i;
if (w83793_bank(dev, 0)) diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index e51fb9c..2299375 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -118,7 +118,7 @@ void intel_prepare_ddi(void)
static void intel_wait_ddi_buf_idle(int port) { - uint32_t reg = DDI_BUF_CTL(port); + u32 reg = DDI_BUF_CTL(port); int i;
for (i = 0; i < 8; i++) { @@ -135,7 +135,7 @@ static void intel_wait_ddi_buf_idle(int port) void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, int port) { int wait = 0; - uint32_t val; + u32 val;
if (gtt_read(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { val = gtt_read(DDI_BUF_CTL(port)); diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c index dc2a957..170692c 100644 --- a/src/drivers/intel/gma/intel_dp.c +++ b/src/drivers/intel/gma/intel_dp.c @@ -72,21 +72,21 @@ static int is_cpu_edp(struct intel_dp *intel_dp) return is_edp(intel_dp) && !is_pch_edp(intel_dp); }
-static uint32_t -pack_aux(uint8_t *src, int src_bytes) +static u32 +pack_aux(u8 *src, int src_bytes) { int i; - uint32_t v = 0; + u32 v = 0;
if (src_bytes > 4) src_bytes = 4; for (i = 0; i < src_bytes; i++) - v |= ((uint32_t) src[i]) << ((3-i) * 8); + v |= ((u32) src[i]) << ((3-i) * 8); return v; }
void -unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) +unpack_aux(u32 src, u8 *dst, int dst_bytes) { int i; if (dst_bytes > 4) @@ -108,15 +108,15 @@ static int ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
int intel_dp_aux_ch(struct intel_dp *intel_dp, - uint8_t *send, int send_bytes, - uint8_t *recv, int recv_size) + u8 *send, int send_bytes, + u8 *recv, int recv_size) { - uint32_t output_reg = intel_dp->output_reg; - uint32_t ch_ctl = output_reg + 0x10; - uint32_t ch_data = ch_ctl + 4; + u32 output_reg = intel_dp->output_reg; + u32 ch_ctl = output_reg + 0x10; + u32 ch_data = ch_ctl + 4; int i; int recv_bytes; - uint32_t status; + u32 status; int try;
/* Try to wait for any previous AUX channel activity */ @@ -213,12 +213,12 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, /* Write data to the aux channel in native mode */ static int intel_dp_aux_native_write(struct intel_dp *intel_dp, - uint16_t address, uint8_t *send, int send_bytes) + u16 address, u8 *send, int send_bytes) { int ret; - uint8_t msg[20]; + u8 msg[20]; int msg_bytes; - uint8_t ack; + u8 ack;
if (send_bytes > 16) return -1; @@ -245,7 +245,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp, /* Write a single byte to the aux channel in native mode */ static int intel_dp_aux_native_write_1(struct intel_dp *intel_dp, - uint16_t address, uint8_t byte) + u16 address, u8 byte) { return intel_dp_aux_native_write(intel_dp, address, &byte, 1); } @@ -287,13 +287,13 @@ int intel_dp_set_training_lane0(struct intel_dp *intel_dp, /* read bytes from a native aux channel */ static int intel_dp_aux_native_read(struct intel_dp *intel_dp, - uint16_t address, uint8_t *recv, int recv_bytes) + u16 address, u8 *recv, int recv_bytes) { - uint8_t msg[4]; + u8 msg[4]; int msg_bytes; - uint8_t reply[20]; + u8 reply[20]; int reply_bytes; - uint8_t ack; + u8 ack; int ret;
msg[0] = AUX_NATIVE_READ << 4; @@ -325,10 +325,10 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
int intel_dp_i2c_aux_ch(struct intel_dp *intel_dp, - int mode, uint8_t write_byte, uint8_t *read_byte) + int mode, u8 write_byte, u8 *read_byte) { - uint8_t msg[5]; - uint8_t reply[2]; + u8 msg[5]; + u8 reply[2]; unsigned retry; int msg_bytes; int reply_bytes; @@ -446,7 +446,7 @@ intel_dp_i2c_init(struct intel_dp *intel_dp) }
static void -intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) +intel_reduce_m_n_ratio(u32 *num, u32 *den) { while (*num > DATA_LINK_M_N_MASK || *den > DATA_LINK_M_N_MASK) { *num >>= 1; @@ -936,8 +936,8 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) * cases where the sink may still be asleep. */ static int -intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, - uint8_t *recv, int recv_bytes) +intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, u16 address, + u8 *recv, int recv_bytes) { int ret, i;
@@ -962,7 +962,7 @@ intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, */ int intel_dp_get_link_status(struct intel_dp *intel_dp, - uint8_t link_status[DP_LINK_STATUS_SIZE]) + u8 link_status[DP_LINK_STATUS_SIZE]) { int ret, i;
@@ -979,8 +979,8 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, return ret; }
-static uint8_t -intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], +static u8 +intel_dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r) { return link_status[r - DP_LANE0_1_STATUS]; @@ -1001,7 +1001,7 @@ const char *link_train_names[] = { * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB */
-static uint8_t +static u8 intel_dp_voltage_max(struct intel_dp *intel_dp) {
@@ -1013,8 +1013,8 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) return DP_TRAIN_VOLTAGE_SWING_800; }
-static uint8_t -intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) +static u8 +intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing) {
if (intel_dp->is_haswell){ @@ -1056,18 +1056,18 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
static void intel_get_adjust_train(struct intel_dp *intel_dp, - uint8_t link_status[DP_LINK_STATUS_SIZE]) + u8 link_status[DP_LINK_STATUS_SIZE]) { - uint8_t v = 0; - uint8_t p = 0; + u8 v = 0; + u8 p = 0; int lane; - uint8_t voltage_max; - uint8_t preemph_max; + u8 voltage_max; + u8 preemph_max;
for (lane = 0; lane < intel_dp->lane_count; lane++) { - uint8_t this_v = drm_dp_get_adjust_request_voltage( + u8 this_v = drm_dp_get_adjust_request_voltage( link_status, lane); - uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis( + u8 this_p = drm_dp_get_adjust_request_pre_emphasis( link_status, lane);
if (this_v > v) @@ -1094,10 +1094,10 @@ intel_get_adjust_train(struct intel_dp *intel_dp, intel_dp->train_set[lane] = v | p; }
-static uint32_t -intel_dp_signal_levels(uint8_t train_set) +static u32 +intel_dp_signal_levels(u8 train_set) { - uint32_t signal_levels = 0; + u32 signal_levels = 0;
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { case DP_TRAIN_VOLTAGE_SWING_400: @@ -1133,8 +1133,8 @@ intel_dp_signal_levels(uint8_t train_set) }
/* Gen6's DP voltage swing and pre-emphasis control */ -static uint32_t -intel_gen6_edp_signal_levels(uint8_t train_set) +static u32 +intel_gen6_edp_signal_levels(u8 train_set) { int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); @@ -1162,8 +1162,8 @@ intel_gen6_edp_signal_levels(uint8_t train_set) }
/* Gen7's DP voltage swing and pre-emphasis control */ -static uint32_t -intel_gen7_edp_signal_levels(uint8_t train_set) +static u32 +intel_gen7_edp_signal_levels(u8 train_set) { int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); @@ -1194,8 +1194,8 @@ intel_gen7_edp_signal_levels(uint8_t train_set) }
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ -static uint32_t -intel_dp_signal_levels_hsw(uint8_t train_set) +static u32 +intel_dp_signal_levels_hsw(u8 train_set) { int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK); @@ -1229,23 +1229,23 @@ intel_dp_signal_levels_hsw(uint8_t train_set) }
-static uint8_t -intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], +static u8 +intel_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], int lane) { int s = (lane & 1) * 4; - uint8_t l = link_status[lane>>1]; + u8 l = link_status[lane>>1];
return (l >> s) & 0xf; }
/* Check for clock recovery is done on all channels */ static int -intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], +intel_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE], int lane_count) { int lane; - uint8_t lane_status; + u8 lane_status;
for (lane = 0; lane < lane_count; lane++) { lane_status = intel_get_lane_status(link_status, lane); @@ -1264,10 +1264,10 @@ intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], DP_LANE_SYMBOL_LOCKED) int intel_channel_eq_ok(struct intel_dp *intel_dp, - uint8_t link_status[DP_LINK_STATUS_SIZE]) + u8 link_status[DP_LINK_STATUS_SIZE]) { - uint8_t lane_align; - uint8_t lane_status; + u8 lane_align; + u8 lane_status; int lane;
lane_align = intel_dp_link_status(link_status, @@ -1284,8 +1284,8 @@ intel_channel_eq_ok(struct intel_dp *intel_dp,
static int intel_dp_set_link_train(struct intel_dp *intel_dp, - uint32_t dp_reg_value, - uint8_t dp_train_pat) + u32 dp_reg_value, + u8 dp_train_pat) { int ret; u32 temp; @@ -1405,11 +1405,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp) { int i; - uint8_t voltage; + u8 voltage; int clock_recovery = 0; int voltage_tries, loop_tries; u32 reg; - uint32_t DP = intel_dp->DP; + u32 DP = intel_dp->DP;
if (intel_dp->is_haswell) intel_ddi_prepare_link_retrain(intel_dp, intel_dp->port); @@ -1431,8 +1431,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
for (;;) { /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ - uint8_t link_status[DP_LINK_STATUS_SIZE]; - uint32_t signal_levels; + u8 link_status[DP_LINK_STATUS_SIZE]; + u32 signal_levels;
if (intel_dp->is_haswell){ signal_levels = diff --git a/src/drivers/maxim/max77686/max77686.c b/src/drivers/maxim/max77686/max77686.c index e971dc5..c5f3369 100644 --- a/src/drivers/maxim/max77686/max77686.c +++ b/src/drivers/maxim/max77686/max77686.c @@ -107,7 +107,7 @@ static inline int max77686_i2c_write(unsigned int bus, unsigned char chip_addr, static inline int max77686_i2c_read(unsigned int bus, unsigned char chip_addr, unsigned int reg, unsigned char *val) { - return i2c_readb(bus, chip_addr, reg, (uint8_t *)val); + return i2c_readb(bus, chip_addr, reg, (u8 *)val); }
/* diff --git a/src/drivers/pc80/spkmodem.c b/src/drivers/pc80/spkmodem.c index 89773b1..9a1e679 100644 --- a/src/drivers/pc80/spkmodem.c +++ b/src/drivers/pc80/spkmodem.c @@ -72,7 +72,7 @@ enum {
static void -make_tone (uint16_t freq_count, unsigned int duration) +make_tone (u16 freq_count, unsigned int duration) { outb (PIT_CTRL_SELECT_2 | PIT_CTRL_READLOAD_WORD @@ -91,7 +91,7 @@ make_tone (uint16_t freq_count, unsigned int duration) unsigned short counter, previous_counter = 0xffff; while (1) { counter = inb (PIT_COUNTER_2); - counter |= ((uint16_t) inb (PIT_COUNTER_2)) << 8; + counter |= ((u16) inb (PIT_COUNTER_2)) << 8; if (counter > previous_counter) { previous_counter = counter; diff --git a/src/drivers/pc80/tpm.c b/src/drivers/pc80/tpm.c index c0429dd..fc8de2b 100644 --- a/src/drivers/pc80/tpm.c +++ b/src/drivers/pc80/tpm.c @@ -662,8 +662,8 @@ int tis_close(void) * Returns 0 on success (and places the number of response bytes at recv_len) * or TPM_DRIVER_ERR on failure. */ -int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, - uint8_t *recvbuf, size_t *recv_len) +int tis_sendrecv(const u8 *sendbuf, size_t send_size, + u8 *recvbuf, size_t *recv_len) { if (tis_senddata(sendbuf, send_size)) { printf("%s:%d failed sending data to TPM\n", diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index 1285726..c5569ed 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -17,7 +17,7 @@
static void si_sata_init(struct device *dev) { - uint32_t dword; + u32 dword; /* enable change device id and class id */ dword = pci_read_config32(dev,0x40); dword |= (1<<0); diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 0fba3e6..1732c36 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -30,12 +30,12 @@ #define CMD_AT25DF_RES 0xab /* Release from DP, and Read Signature */
struct adesto_spi_flash_params { - uint16_t id; + u16 id; /* Log2 of page size in power-of-two mode */ - uint8_t l2_page_size; - uint16_t pages_per_sector; - uint16_t sectors_per_block; - uint16_t nr_blocks; + u8 l2_page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_blocks; const char *name; };
diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 87ef951..58487ff 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -28,12 +28,12 @@ #define CMD_A25_RES 0xab /* Release from DP, and Read Signature */
struct amic_spi_flash_params { - uint16_t id; + u16 id; /* Log2 of page size in power-of-two mode */ - uint8_t l2_page_size; - uint16_t pages_per_sector; - uint16_t sectors_per_block; - uint16_t nr_blocks; + u8 l2_page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_blocks; const char *name; };
diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 4a0dc35..f492fb3 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -25,12 +25,12 @@ #define CMD_AT25_RES 0xab /* Release from DP, and Read Signature */
struct atmel_spi_flash_params { - uint16_t id; + u16 id; /* Log2 of page size in power-of-two mode */ - uint8_t l2_page_size; - uint16_t pages_per_sector; - uint16_t sectors_per_block; - uint16_t nr_blocks; + u8 l2_page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_blocks; const char *name; };
diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 68b487e..cb83bb2 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -46,12 +46,12 @@ #define CMD_GD25_RES 0xab /* Release from DP, and Read Signature */
struct gigadevice_spi_flash_params { - uint16_t id; + u16 id; /* Log2 of page size in power-of-two mode */ - uint8_t l2_page_size; - uint16_t pages_per_sector; - uint16_t sectors_per_block; - uint16_t nr_blocks; + u8 l2_page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_blocks; const char *name; };
diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 4c4150f..9f95660 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -24,12 +24,12 @@ #define CMD_W25_RES 0xab /* Release from DP, and Read Signature */
struct winbond_spi_flash_params { - uint16_t id; + u16 id; /* Log2 of page size in power-of-two mode */ - uint8_t l2_page_size; - uint16_t pages_per_sector; - uint16_t sectors_per_block; - uint16_t nr_blocks; + u8 l2_page_size; + u16 pages_per_sector; + u16 sectors_per_block; + u16 nr_blocks; const char *name; };
diff --git a/src/drivers/ti/tps65090/tps65090.c b/src/drivers/ti/tps65090/tps65090.c index 35a050f..0a28c132 100644 --- a/src/drivers/ti/tps65090/tps65090.c +++ b/src/drivers/ti/tps65090/tps65090.c @@ -95,7 +95,7 @@ static int tps65090_i2c_read(unsigned int bus, static int tps65090_fet_set(unsigned int bus, enum fet_id fet_id, int set) { int retry, value; - uint8_t reg; + u8 reg;
value = FET_CTRL_ADENFET | FET_CTRL_WAIT; if (set) diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 5fbbeec..1ca23c2 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -34,12 +34,12 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
-static uint8_t uart8250_read(void *base, uint8_t reg) +static u8 uart8250_read(void *base, u8 reg) { return read8((uintptr_t) (base + reg)); }
-static void uart8250_write(void *base, uint8_t reg, uint8_t data) +static void uart8250_write(void *base, u8 reg, u8 data) { write8((uintptr_t) (base + reg), data); } diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index 42c7c2e..4b96f56 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -35,7 +35,7 @@ * @param data Data buffer to print. * @param len Length of data. */ -static void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, +static void cros_ec_dump_data(const char *name, int cmd, const u8 *data, int len) { int i; @@ -54,7 +54,7 @@ static void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, * @param size Size of data block in bytes * @return checksum value (0 to 255) */ -static int cros_ec_calc_checksum(const uint8_t *data, int size) +static int cros_ec_calc_checksum(const u8 *data, int size) { int csum, i;
@@ -67,12 +67,12 @@ static int cros_ec_calc_checksum(const uint8_t *data, int size)
struct ec_command_v3 { struct ec_host_request header; - uint8_t data[MSG_BYTES]; + u8 data[MSG_BYTES]; };
struct ec_response_v3 { struct ec_host_response header; - uint8_t data[MSG_BYTES]; + u8 data[MSG_BYTES]; };
/** @@ -107,10 +107,10 @@ static int create_proto3_request(const struct chromeec_command *cec_command, memcpy(cmd->data, cec_command->cmd_data_in, cec_command->cmd_size_in);
/* Write checksum field so the entire packet sums to 0 */ - rq->checksum = (uint8_t)(-cros_ec_calc_checksum( - (const uint8_t*)cmd, out_bytes)); + rq->checksum = (u8)(-cros_ec_calc_checksum( + (const u8*)cmd, out_bytes));
- cros_ec_dump_data("out", rq->command, (const uint8_t *)cmd, out_bytes); + cros_ec_dump_data("out", rq->command, (const u8 *)cmd, out_bytes);
/* Return size of request packet */ return out_bytes; @@ -156,7 +156,7 @@ static int handle_proto3_response(struct ec_response_v3 *resp, int in_bytes; int csum;
- cros_ec_dump_data("in-header", -1, (const uint8_t*)rs, sizeof(*rs)); + cros_ec_dump_data("in-header", -1, (const u8*)rs, sizeof(*rs));
/* Check input data */ if (rs->struct_version != EC_HOST_RESPONSE_VERSION) { @@ -181,7 +181,7 @@ static int handle_proto3_response(struct ec_response_v3 *resp, in_bytes = sizeof(*rs) + rs->data_len;
/* Verify checksum */ - csum = cros_ec_calc_checksum((const uint8_t *)resp, in_bytes); + csum = cros_ec_calc_checksum((const u8 *)resp, in_bytes); if (csum) { printk(BIOS_ERR, "%s: EC response checksum invalid: 0x%02x\n", __func__, csum); @@ -223,7 +223,7 @@ static int send_command_proto3(struct chromeec_command *cec_command, return in_bytes; }
- rv = crosec_io((uint8_t *)&cmd, out_bytes, (uint8_t *)&resp, in_bytes, + rv = crosec_io((u8 *)&cmd, out_bytes, (u8 *)&resp, in_bytes, context); if (rv != 0) { printk(BIOS_ERR, "%s: failed to complete I/O: Err = %#x.", diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 9e6e4d6..bc9c57c 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -32,13 +32,13 @@ #include "ec.h" #include "ec_commands.h"
-uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size) +u8 google_chromeec_calc_checksum(const u8 *data, int size) { int csum;
for (csum = 0; size > 0; data++, size--) csum += *data; - return (uint8_t)(csum & 0xff); + return (u8)(csum & 0xff); }
int google_chromeec_kbbacklight(int percent) @@ -179,7 +179,7 @@ u16 google_chromeec_get_board_version(void) return board_v.board_version; }
-int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len) +int google_chromeec_vbnv_context(int is_read, u8 *data, int len) { struct chromeec_command cec_cmd; struct ec_params_vbnvcontext cmd_vbnvcontext; @@ -214,22 +214,22 @@ int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
#ifndef __PRE_RAM__
-int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, - uint8_t *buffer, int len, int is_read) +int google_chromeec_i2c_xfer(u8 chip, u8 addr, int alen, + u8 *buffer, int len, int is_read) { union { struct ec_params_i2c_passthru p; - uint8_t outbuf[EC_HOST_PARAM_SIZE]; + u8 outbuf[EC_HOST_PARAM_SIZE]; } params; union { struct ec_response_i2c_passthru r; - uint8_t inbuf[EC_HOST_PARAM_SIZE]; + u8 inbuf[EC_HOST_PARAM_SIZE]; } response; struct ec_params_i2c_passthru *p = ¶ms.p; struct ec_response_i2c_passthru *r = &response.r; struct ec_params_i2c_passthru_msg *msg = p->msg; struct chromeec_command cmd; - uint8_t *pdata; + u8 *pdata; int read_len, write_len; int size; int rv; @@ -261,7 +261,7 @@ int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, }
/* Create a message to write the register address and optional data */ - pdata = (uint8_t *)p + size; + pdata = (u8 *)p + size; msg->addr_flags = chip; msg->len = write_len; pdata[0] = addr; diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index 551c3b9..90c675b 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -42,19 +42,19 @@ #define MAX_I2C_DATA_SIZE (0xff)
typedef struct { - uint8_t version; - uint8_t command; - uint8_t length; - uint8_t data[MAX_I2C_DATA_SIZE + 1]; + u8 version; + u8 command; + u8 length; + u8 data[MAX_I2C_DATA_SIZE + 1]; } EcCommandI2c;
typedef struct { - uint8_t response; - uint8_t length; - uint8_t data[MAX_I2C_DATA_SIZE + 1]; + u8 response; + u8 length; + u8 data[MAX_I2C_DATA_SIZE + 1]; } EcResponseI2c;
-static inline void i2c_dump(int bus, int chip, const uint8_t *data, size_t size) +static inline void i2c_dump(int bus, int chip, const u8 *data, size_t size) { #ifdef TRACE_CHROMEEC printk(BIOS_INFO, "i2c: bus=%d, chip=%#x, size=%d, data: ", bus, chip, @@ -69,9 +69,9 @@ static inline void i2c_dump(int bus, int chip, const uint8_t *data, size_t size) static int ec_verify_checksum(const EcResponseI2c *resp) { size_t size = sizeof(*resp) - sizeof(resp->data) + resp->length; - uint8_t calculated = google_chromeec_calc_checksum( - (const uint8_t *)resp, size); - uint8_t received = resp->data[resp->length]; + u8 calculated = google_chromeec_calc_checksum( + (const u8 *)resp, size); + u8 received = resp->data[resp->length]; if (calculated != received) { printk(BIOS_ERR, "%s: Unmatch (rx: %#02x, calc: %#02x)\n", __func__, received, calculated); @@ -84,7 +84,7 @@ static void ec_fill_checksum(EcCommandI2c *cmd) { size_t size = sizeof(*cmd) - sizeof(cmd->data) + cmd->length; cmd->data[cmd->length] = google_chromeec_calc_checksum( - (const uint8_t *)cmd, size); + (const u8 *)cmd, size); }
int google_chromeec_command(struct chromeec_command *cec_command) @@ -115,14 +115,14 @@ int google_chromeec_command(struct chromeec_command *cec_command) ec_fill_checksum(&cmd);
/* Start I2C communication */ - i2c_dump(bus, chip, (const uint8_t *)&cmd, size_i2c_cmd); - if (i2c_write_raw(bus, chip, (uint8_t *)&cmd, size_i2c_cmd) != 0) { + i2c_dump(bus, chip, (const u8 *)&cmd, size_i2c_cmd); + if (i2c_write_raw(bus, chip, (u8 *)&cmd, size_i2c_cmd) != 0) { printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n", __func__, bus, chip); cec_command->cmd_code = EC_RES_ERROR; return 1; } - if (i2c_read_raw(bus, chip, (uint8_t *)&resp, size_i2c_resp) != 0) { + if (i2c_read_raw(bus, chip, (u8 *)&resp, size_i2c_resp) != 0) { printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n", __func__, bus, chip); cec_command->cmd_code = EC_RES_ERROR; diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index f1bdd3c..03774bf 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -23,10 +23,10 @@ #include <spi-generic.h> #include <timer.h>
-static const uint8_t EcFramingByte = 0xec; +static const u8 EcFramingByte = 0xec;
-static int crosec_spi_io(uint8_t *write_bytes, size_t write_size, - uint8_t *read_bytes, size_t read_size, +static int crosec_spi_io(u8 *write_bytes, size_t write_size, + u8 *read_bytes, size_t read_size, void *context) { struct spi_slave *slave = (struct spi_slave *)context; @@ -39,7 +39,7 @@ static int crosec_spi_io(uint8_t *write_bytes, size_t write_size, return -1; }
- uint8_t byte; + u8 byte; struct mono_time start; struct rela_time rt; timer_monotonic_get(&start); diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index f1bd7cc..aff471b 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -45,7 +45,7 @@ void bootmem_init(void) cbmem_add_bootmem(); }
-void bootmem_add_range(uint64_t start, uint64_t size, uint32_t type) +void bootmem_add_range(u64 start, u64 size, u32 type) { memranges_insert(&bootmem, start, size, type); } @@ -110,10 +110,10 @@ void bootmem_dump_ranges(void) } }
-int bootmem_region_targets_usable_ram(uint64_t start, uint64_t size) +int bootmem_region_targets_usable_ram(u64 start, u64 size) { const struct range_entry *r; - uint64_t end = start + size; + u64 end = start + size;
memranges_each_entry(r, &bootmem) { /* All further bootmem entries are beyond this range. */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9e9f4a7..eccc73c 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -35,12 +35,12 @@ static void tohex16(unsigned int val, char* dest) dest[3] = tohex4(val & 0xf); }
-void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, - uint16_t device, void *dest) +void *cbfs_load_optionrom(struct cbfs_media *media, u16 vendor, + u16 device, void *dest) { char name[17] = "pciXXXX,XXXX.rom"; struct cbfs_optionrom *orom; - uint8_t *src; + u8 *src;
tohex16(vendor, name+3); tohex16(device, name+8); @@ -59,7 +59,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, */
/* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */ - src = (uint8_t *)orom; // + sizeof(struct cbfs_optionrom); + src = (u8 *)orom; // + sizeof(struct cbfs_optionrom);
if (! dest) return src; @@ -80,7 +80,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ uintptr_t entry; - uint32_t final_size; + u32 final_size;
if (stage == NULL) return (void *) -1; diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 0f97755..8fe18a5 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -97,7 +97,7 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) { const char *file_name; - uint32_t offset, align, romsize, name_len; + u32 offset, align, romsize, name_len; const struct cbfs_header *header; struct cbfs_file file, *file_ptr; struct cbfs_media default_media; @@ -142,7 +142,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { if (memcmp(CBFS_FILE_MAGIC, file.magic, sizeof(file.magic)) != 0) { - uint32_t new_align = align; + u32 new_align = align; if (offset % align) new_align += align - (offset % align); ERROR("ERROR: No file header found at 0x%x - " diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 0b24ad2..b6cc6f5 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -44,11 +44,11 @@ struct cbmem_entry { } __attribute__((packed));
#ifndef __PRE_RAM__ -static uint64_t cbmem_base = 0; -static uint64_t cbmem_size = 0; +static u64 cbmem_base = 0; +static u64 cbmem_size = 0; #endif
-static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) +static void cbmem_trace_location(u64 base, u64 size, const char *s) { if (base && size && s) { printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", @@ -56,7 +56,7 @@ static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) } }
-static void cbmem_locate_table(uint64_t *base, uint64_t *size) +static void cbmem_locate_table(u64 *base, u64 *size) { #ifdef __PRE_RAM__ get_cbmem_table(base, size); @@ -72,13 +72,13 @@ static void cbmem_locate_table(uint64_t *base, uint64_t *size)
struct cbmem_entry *get_cbmem_toc(void) { - uint64_t base, size; + u64 base, size; cbmem_locate_table(&base, &size); return (struct cbmem_entry *)(unsigned long)base; }
#if !defined(__PRE_RAM__) -void cbmem_late_set_table(uint64_t base, uint64_t size) +void cbmem_late_set_table(u64 base, u64 size) { cbmem_trace_location(base, size, __FUNCTION__); cbmem_base = base; @@ -98,7 +98,7 @@ void cbmem_late_set_table(uint64_t base, uint64_t size)
static void cbmem_initialize_empty(void) { - uint64_t baseaddr, size; + u64 baseaddr, size; struct cbmem_entry *cbmem_toc;
cbmem_locate_table(&baseaddr, &size); @@ -122,7 +122,7 @@ static void cbmem_initialize_empty(void)
static int cbmem_check_toc(void) { - uint64_t baseaddr, size; + u64 baseaddr, size; struct cbmem_entry *cbmem_toc;
cbmem_locate_table(&baseaddr, &size); diff --git a/src/lib/compute_ip_checksum.c b/src/lib/compute_ip_checksum.c index 58a6bf1..4415ef3 100644 --- a/src/lib/compute_ip_checksum.c +++ b/src/lib/compute_ip_checksum.c @@ -3,10 +3,10 @@
unsigned long compute_ip_checksum(void *addr, unsigned long length) { - uint8_t *ptr; + u8 *ptr; volatile union { - uint8_t byte[2]; - uint16_t word; + u8 byte[2]; + u16 word; } value; unsigned long sum; unsigned long i; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 12090dc..3b5b781 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -115,7 +115,7 @@ void lb_add_serial(struct lb_serial *new_serial, void *data) serial->baud = new_serial->baud; }
-void lb_add_console(uint16_t consoletype, void *data) +void lb_add_console(u16 consoletype, void *data) { struct lb_header *header = (struct lb_header *)data; struct lb_console *console; @@ -195,7 +195,7 @@ static void lb_vbnv(struct lb_header *header) static void lb_vboot_handoff(struct lb_header *header) { void *addr; - uint32_t size; + u32 size; struct lb_range *vbho;
if (vboot_get_handoff_info(&addr, &size)) @@ -274,7 +274,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header) static void lb_strings(struct lb_header *header) { static const struct { - uint32_t tag; + u32 tag; const char *string; } strings[] = { { LB_TAG_VERSION, coreboot_version, }, @@ -317,7 +317,7 @@ static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header forward = (struct lb_forward *)rec; forward->tag = LB_TAG_FORWARD; forward->size = sizeof(*forward); - forward->forward = (uint64_t)(unsigned long)next_header; + forward->forward = (u64)(unsigned long)next_header; return forward; }
@@ -386,7 +386,7 @@ unsigned long write_coreboot_table( bootmem_init();
if (low_table_start || low_table_end) { - uint64_t size = low_table_end - low_table_start; + u64 size = low_table_end - low_table_start; /* Record the mptable and the the lb_table. * (This will be adjusted later) */ bootmem_add_range(low_table_start, size, LB_MEM_TABLE); @@ -397,7 +397,7 @@ unsigned long write_coreboot_table( * 1MiB. If it isn't that means high tables are being written. * The code below handles high tables correctly. */ if (rom_table_end <= (1 << 20)) { - uint64_t size = rom_table_end - rom_table_start; + u64 size = rom_table_end - rom_table_start; bootmem_add_range(rom_table_start, size, LB_MEM_TABLE); }
diff --git a/src/lib/edid.c b/src/lib/edid.c index 4d2d55d..30fe3ee 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1194,7 +1194,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
printk(BIOS_SPEW, "Standard timings supported:\n"); for (i = 0; i < 8; i++) { - uint8_t b1 = edid[0x26 + i * 2], b2 = edid[0x26 + i * 2 + 1]; + u8 b1 = edid[0x26 + i * 2], b2 = edid[0x26 + i * 2 + 1]; unsigned int x, y = 0, refresh;
if (b1 == 0x01 && b2 == 0x01) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index ab9062b..9649a6b 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -22,7 +22,7 @@ #include <cbmem.h>
typedef struct file { - uint32_t magic; + u32 magic; struct file *next; char *filename; char *data; diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c index efb61db..6131f66 100644 --- a/src/lib/generic_sdram.c +++ b/src/lib/generic_sdram.c @@ -1,6 +1,6 @@ #include <lib.h> /* Prototypes */
-static inline void print_debug_sdram_8(const char *strval, uint32_t val) +static inline void print_debug_sdram_8(const char *strval, u32 val) { #if CONFIG_CACHE_AS_RAM printk(BIOS_DEBUG, "%s%02x\n", strval, val); diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index a15c5cd..2fcf1e1 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -31,10 +31,10 @@ static int isprint(int c) void hexdump(const void *memory, size_t length) { int i; - uint8_t *m; + u8 *m; int all_zero = 0;
- m = (uint8_t *) memory; + m = (u8 *) memory;
for (i = 0; i < length; i += 16) { int j; diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c index 5d5cc0b..fa7c8e0 100644 --- a/src/lib/loaders/cbfs_ramstage_loader.c +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -26,7 +26,7 @@ #if CONFIG_RELOCATABLE_RAMSTAGE #include <rmodule.h>
-static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, +static void *cbfs_load_ramstage(u32 cbmem_id, const char *name, const struct cbmem_entry **cbmem_entry) { struct rmod_stage_load rmod_ram = { @@ -46,7 +46,7 @@ static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name,
#else /* CONFIG_RELOCATABLE_RAMSTAGE */
-static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, +static void *cbfs_load_ramstage(u32 cbmem_id, const char *name, const struct cbmem_entry **cbmem_entry) { void *entry; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index 71eb22c..956d4f8 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -37,7 +37,7 @@ static const struct ramstage_loader_ops *loaders[] = { };
static const char *ramstage_name = CONFIG_CBFS_PREFIX "/ramstage"; -static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; +static const u32 ramstage_id = CBMEM_ID_RAMSTAGE;
static void load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) diff --git a/src/lib/ramstage_cache.c b/src/lib/ramstage_cache.c index 814d807..9aaae8e 100644 --- a/src/lib/ramstage_cache.c +++ b/src/lib/ramstage_cache.c @@ -31,8 +31,8 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, void *entry_point) { struct ramstage_cache *cache; - uint32_t total_size; - uint32_t ramstage_size; + u32 total_size; + u32 ramstage_size; void *ramstage_base; long cache_size = 0;
@@ -56,8 +56,8 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, }
cache->magic = RAMSTAGE_CACHE_MAGIC; - cache->entry_point = (uint32_t)entry_point; - cache->load_address = (uint32_t)ramstage_base; + cache->entry_point = (u32)entry_point; + cache->load_address = (u32)ramstage_base; cache->size = ramstage_size;
printk(BIOS_DEBUG, "Saving ramstage to %p.\n", cache); @@ -68,7 +68,7 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, if (handoff == NULL) return;
- handoff->ramstage_entry_point = (uint32_t)entry_point; + handoff->ramstage_entry_point = (u32)entry_point; }
void *load_cached_ramstage(struct romstage_handoff *handoff, @@ -99,7 +99,7 @@ void *load_cached_ramstage(struct romstage_handoff *handoff, void cache_loaded_ramstage(struct romstage_handoff *handoff, const struct cbmem_entry *ramstage, void *entry_point) { - uint32_t ramstage_size; + u32 ramstage_size; const struct cbmem_entry *entry;
if (handoff == NULL) @@ -113,7 +113,7 @@ void cache_loaded_ramstage(struct romstage_handoff *handoff, return;
/* Keep track of the entry point in the handoff structure. */ - handoff->ramstage_entry_point = (uint32_t)entry_point; + handoff->ramstage_entry_point = (u32)entry_point;
memcpy(cbmem_entry_start(entry), cbmem_entry_start(ramstage), ramstage_size); diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index e9173fa..4a0de77 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -59,7 +59,7 @@ static void phys_memory_barrier(void) static inline void test_pattern(unsigned short int idx, unsigned long *addr, unsigned long *value) { - uint8_t j, k; + u8 j, k;
k = (idx >> 8) + 1; j = (idx >> 4) & 0x0f; @@ -81,7 +81,7 @@ static int ram_bitset_nodie(unsigned long start) unsigned long addr, value, value2; unsigned short int idx; unsigned char failed, failures; - uint8_t verbose = 0; + u8 verbose = 0;
#if !defined(__ROMCC__) printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start); diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 647723b..2eabbc7 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -85,7 +85,7 @@ static struct resource *reg_script_get_resource(struct reg_script_context *ctx) #endif }
-static uint32_t reg_script_read_pci(struct reg_script_context *ctx) +static u32 reg_script_read_pci(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx);
@@ -117,7 +117,7 @@ static void reg_script_write_pci(struct reg_script_context *ctx) } }
-static uint32_t reg_script_read_io(struct reg_script_context *ctx) +static u32 reg_script_read_io(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx);
@@ -149,7 +149,7 @@ static void reg_script_write_io(struct reg_script_context *ctx) } }
-static uint32_t reg_script_read_mmio(struct reg_script_context *ctx) +static u32 reg_script_read_mmio(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx);
@@ -181,10 +181,10 @@ static void reg_script_write_mmio(struct reg_script_context *ctx) } }
-static uint32_t reg_script_read_res(struct reg_script_context *ctx) +static u32 reg_script_read_res(struct reg_script_context *ctx) { struct resource *res; - uint32_t val = 0; + u32 val = 0; const struct reg_script *step = reg_script_get_step(ctx);
res = reg_script_get_resource(ctx); @@ -243,7 +243,7 @@ static void reg_script_write_res(struct reg_script_context *ctx) reg_script_set_step(ctx, step); }
-static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) +static u32 reg_script_read_iosf(struct reg_script_context *ctx) { #if CONFIG_SOC_INTEL_BAYTRAIL const struct reg_script *step = reg_script_get_step(ctx); @@ -377,12 +377,12 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) #endif }
-static uint64_t reg_script_read_msr(struct reg_script_context *ctx) +static u64 reg_script_read_msr(struct reg_script_context *ctx) { #if CONFIG_ARCH_X86 const struct reg_script *step = reg_script_get_step(ctx); msr_t msr = rdmsr(step->reg); - uint64_t value = msr.hi; + u64 value = msr.hi; value = msr.hi; value <<= 32; value |= msr.lo; @@ -401,7 +401,7 @@ static void reg_script_write_msr(struct reg_script_context *ctx) #endif }
-static uint64_t reg_script_read(struct reg_script_context *ctx) +static u64 reg_script_read(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx);
@@ -450,7 +450,7 @@ static void reg_script_write(struct reg_script_context *ctx)
static void reg_script_rmw(struct reg_script_context *ctx) { - uint64_t value; + u64 value; const struct reg_script *step = reg_script_get_step(ctx); struct reg_script write_step = *step;
@@ -474,7 +474,7 @@ static void reg_script_run_next(struct reg_script_context *ctx, static void reg_script_run_step(struct reg_script_context *ctx, const struct reg_script *step) { - uint64_t value = 0, try; + u64 value = 0, try;
switch (step->command) { case REG_SCRIPT_COMMAND_READ: diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index f0ee48d..8b407a4 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -32,9 +32,9 @@ static tsc_t ts_basetime CAR_GLOBAL = { .lo = 0, .hi =0 };
static void timestamp_stash(enum timestamp_id id, tsc_t ts_time);
-static uint64_t tsc_to_uint64(tsc_t tstamp) +static u64 tsc_to_uint64(tsc_t tstamp) { - return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; + return (((u64)tstamp.hi) << 32) + tstamp.lo; }
static void timestamp_real_init(tsc_t base) diff --git a/src/lib/trace.c b/src/lib/trace.c index 185e6c8..bd4052e 100644 --- a/src/lib/trace.c +++ b/src/lib/trace.c @@ -30,7 +30,7 @@ void __cyg_profile_func_enter( void *func, void *callsite) return;
DISABLE_TRACE - printk(BIOS_INFO, "~0x%08x(0x%08x)\n", (uint32_t) func, (uint32_t) callsite); + printk(BIOS_INFO, "~0x%08x(0x%08x)\n", (u32) func, (u32) callsite); ENABLE_TRACE }
diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index 4d42f47..cae97e0 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -13,9 +13,12 @@
#include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -42,9 +45,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum=0; + u8 sum=0; int i;
struct mb_sysconf_t *m; @@ -61,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index ec0682a..1d44708 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -68,7 +68,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 443fdc5..0410423 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -231,8 +231,8 @@ static void rcba_config(void)
static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32;
// program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 6ee2704..a3148e1 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -21,7 +21,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0xff; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; + u32 config_map; unsigned dst_node; unsigned dst_link; unsigned bus_base; @@ -207,7 +207,7 @@ static void reboot_if_hotswap(void) { /* Hack patch work around for hot swap enable 33mhz problem */ device_t dev; - uint32_t data; + u32 data; unsigned long htic; int reset;
diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 3c7eb58..f442468 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -63,7 +63,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 diff --git a/src/mainboard/asus/a8n_e/irq_tables.c b/src/mainboard/asus/a8n_e/irq_tables.c index 6379b93..4c956ca 100644 --- a/src/mainboard/asus/a8n_e/irq_tables.c +++ b/src/mainboard/asus/a8n_e/irq_tables.c @@ -35,11 +35,11 @@ extern unsigned char bus_ck804[6]; /** * Add one line to IRQ table. */ -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, + u8 devfn, u8 link0, u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, + u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -64,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num, sbdn; - uint8_t *v, sum = 0; + u8 *v, sum = 0; int i;
/* get_bus_conf() will find out all bus num and APIC that share with @@ -81,7 +81,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c index a954d92..33e706d 100644 --- a/src/mainboard/asus/a8n_e/mptable.c +++ b/src/mainboard/asus/a8n_e/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); if (dev) { diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index c0fa6a5..0a78a98 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -66,8 +66,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
/* Subject decoding */ byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b); @@ -82,7 +82,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 0d55e53..85774fa 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <reset.h> void soft_reset(void) { - uint8_t tmp; + u8 tmp;
set_bios_reset(); print_debug("soft reset\n"); @@ -139,7 +139,7 @@ static void sio_init(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 3ed2491..c4c7e35 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <reset.h> void soft_reset(void) { - uint8_t tmp; + u8 tmp;
set_bios_reset(); print_debug("soft reset\n"); @@ -139,7 +139,7 @@ static void sio_init(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, 0, 0, 0, 0, diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index dab3193..283ca9a 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -60,7 +60,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include <reset.h> void soft_reset(void) { - uint8_t tmp; + u8 tmp;
set_bios_reset(); print_debug("soft reset\n"); @@ -95,7 +95,7 @@ unsigned int get_sbdn(unsigned bus)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // Node 0 DIMM0, DIMM1, DIMM2, 0, 0, 0, 0, 0, diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 42b03c8..f8bf3b2 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -89,7 +89,7 @@ static void ldtstop_sb(void)
void soft_reset(void) { - uint8_t tmp; + u8 tmp;
set_bios_reset(); print_debug("soft reset\n"); @@ -114,7 +114,7 @@ unsigned int get_sbdn(unsigned bus)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index f776351..31e72ec 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -73,7 +73,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void soft_reset(void) { - uint8_t tmp; + u8 tmp;
set_bios_reset(); print_debug("soft reset\n"); @@ -211,7 +211,7 @@ static void m2v_bus_init(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c index 574e9a6..a6ba4c0 100644 --- a/src/mainboard/bifferos/bifferboard/romstage.c +++ b/src/mainboard/bifferos/bifferboard/romstage.c @@ -28,7 +28,7 @@
static void main(void) { - uint32_t tmp; + u32 tmp; post_code(0x05);
/* Set timer1 to pulse generator 15us for memory refresh */ diff --git a/src/mainboard/broadcom/blast/irq_tables.c b/src/mainboard/broadcom/blast/irq_tables.c index 1f39adf..92c23bb 100644 --- a/src/mainboard/broadcom/blast/irq_tables.c +++ b/src/mainboard/broadcom/blast/irq_tables.c @@ -12,9 +12,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -47,9 +50,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); @@ -62,7 +65,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index d7ae6b7..0cd7cdc 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -73,7 +73,7 @@ static void *smp_write_config_table(void *v) device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0x6c); dword |= (1<<4); // enable interrupts pci_write_config32(dev, 0x6c, dword); diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 03cdc1d..94e1c3a 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, RC1|DIMM0, RC1|DIMM2, 0, 0, diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 44256be..7d5a3e2 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -143,7 +143,7 @@ int fw_cfg_max_cpus(void) #define BIOS_LINKER_LOADER_FILESZ 56
struct BiosLinkerLoaderEntry { - uint32_t command; + u32 command; union { /* * COMMAND_ALLOCATE - allocate a table from @alloc.file @@ -155,8 +155,8 @@ struct BiosLinkerLoaderEntry { */ struct { char file[BIOS_LINKER_LOADER_FILESZ]; - uint32_t align; - uint8_t zone; + u32 align; + u8 zone; } alloc;
/* @@ -168,8 +168,8 @@ struct BiosLinkerLoaderEntry { struct { char dest_file[BIOS_LINKER_LOADER_FILESZ]; char src_file[BIOS_LINKER_LOADER_FILESZ]; - uint32_t offset; - uint8_t size; + u32 offset; + u8 size; } pointer;
/* @@ -181,9 +181,9 @@ struct BiosLinkerLoaderEntry { */ struct { char file[BIOS_LINKER_LOADER_FILESZ]; - uint32_t offset; - uint32_t start; - uint32_t length; + u32 offset; + u32 start; + u32 length; } cksum;
/* padding */ @@ -207,8 +207,8 @@ unsigned long fw_cfg_acpi_tables(unsigned long start) { BiosLinkerLoaderEntry *s; unsigned long *addrs, current; - uint32_t *ptr4; - uint64_t *ptr8; + u32 *ptr4; + u64 *ptr8; int rc, i, j, src, dst, max;
rc = fw_cfg_check_file("etc/table-loader"); @@ -252,12 +252,12 @@ unsigned long fw_cfg_acpi_tables(unsigned long start)
switch (s[i].pointer.size) { case 4: - ptr4 = (uint32_t*)(addrs[dst] + s[i].pointer.offset); + ptr4 = (u32*)(addrs[dst] + s[i].pointer.offset); *ptr4 += addrs[src]; break;
case 8: - ptr8 = (uint64_t*)(addrs[dst] + s[i].pointer.offset); + ptr8 = (u64*)(addrs[dst] + s[i].pointer.offset); *ptr8 += addrs[src]; break;
@@ -284,7 +284,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start) if (dst == -1) goto err;
- ptr4 = (uint32_t*)(addrs[dst] + s[i].cksum.offset); + ptr4 = (u32*)(addrs[dst] + s[i].cksum.offset); *ptr4 = 0; *ptr4 = acpi_checksum((void *)(addrs[dst] + s[i].cksum.start), s[i].cksum.length); @@ -322,7 +322,7 @@ static u8 type1_uuid[16]; static void fw_cfg_smbios_init(void) { static int done = 0; - uint16_t i, count = 0; + u16 i, count = 0; FwCfgSmbios entry; char *buf;
diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index a8a61c4..f85425c 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -34,7 +34,7 @@ static void qemu_nb_init(device_t dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; - uint8_t v = pci_read_config8(dev, 0x59); + u8 v = pci_read_config8(dev, 0x59); v |= 0x30; pci_write_config8(dev, 0x59, v); for (i=0; i<6; i++) diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 939a4e6..07c22fa 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -6,7 +6,7 @@
static void bootblock_northbridge_init(void) { - uint32_t reg; + u32 reg;
/* * The "io" variant of the config access is explicitly used to diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index e991b53..d541488 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -37,7 +37,7 @@ static void qemu_nb_init(device_t dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; - uint8_t v = pci_read_config8(dev, Q35_PAM0); + u8 v = pci_read_config8(dev, Q35_PAM0); v |= 0x30; pci_write_config8(dev, Q35_PAM0, v); pci_write_config8(dev, Q35_PAM0 + 1, 0x33); diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 6647cde..ba9f235 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include <boot/coreboot_tables.h>
-static uint8_t *buf = (void *)0x3f8; +static u8 *buf = (void *)0x3f8; uintptr_t uart_platform_base(int idx) { return (uintptr_t) buf; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index b57e6b7..2e4c4a7 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -211,8 +211,8 @@ static void rcba_config(void)
static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32;
// program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c index 97746ec..59cedf2 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c @@ -35,9 +35,12 @@ #include <device/pci_ids.h> #include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,10 +63,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -77,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; @@ -130,8 +133,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) PINTH = IRQ7
*/ - uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63}; - uint8_t irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07}; + u8 reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63}; + u8 irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07};
for(i=0;i<8;i++) pci_write_config8(dev, reg[i], irq[i]); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 0af6cf0..7dcb444 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -53,7 +53,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 10bbb6f..005f02f 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -85,8 +85,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; @@ -103,7 +103,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c index 07a2666..9adb7fe 100644 --- a/src/mainboard/gigabyte/m57sli/fanctl.c +++ b/src/mainboard/gigabyte/m57sli/fanctl.c @@ -2,14 +2,14 @@ #include <stdlib.h> #include <superio/ite/it8716f/it8716f.h>
-static void write_index(uint16_t port_base, uint8_t reg, uint8_t value) +static void write_index(u16 port_base, u8 reg, u8 value) { outb(reg, port_base); outb(value, port_base + 1); }
static const struct { - uint8_t index, value; + u8 index, value; } sequence[]= { /* Make sure we can monitor, and enable SMI# interrupt output */ { 0x00, 0x13}, @@ -72,7 +72,7 @@ static const struct { /* * Called from superio.c */ -void init_ec(uint16_t base) +void init_ec(u16 base) { int i; for (i=0; i<ARRAY_SIZE(sequence); i++) { diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c index e8a1ea0..c0de5a3 100644 --- a/src/mainboard/gigabyte/m57sli/irq_tables.c +++ b/src/mainboard/gigabyte/m57sli/irq_tables.c @@ -33,9 +33,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,10 +63,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -77,7 +80,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b2e1d70..26b3148 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -76,8 +76,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; @@ -94,7 +94,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index f7443be..91ed23c 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -84,7 +84,7 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void) { - uint32_t ec_events; + u32 ec_events;
/* The GPIO is active low. */ if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO diff --git a/src/mainboard/google/nyan/boardid.c b/src/mainboard/google/nyan/boardid.c index 18d920b..47f547e 100644 --- a/src/mainboard/google/nyan/boardid.c +++ b/src/mainboard/google/nyan/boardid.c @@ -22,7 +22,7 @@
#include "boardid.h"
-uint8_t board_id(void) +u8 board_id(void) { static int id = -1;
diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 6377fb2..887dfd0 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -82,7 +82,7 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void) { - uint32_t ec_events; + u32 ec_events;
/* The GPIO is active low. */ if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 682fdc4..2f34358 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -96,7 +96,7 @@ static void setup_pinmux(void)
// TODO(hungte) Revice pinmux setup, make nice little SoC functions for // every single logical thing instead of dumping a wall of code below. - uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, + u32 pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE, pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c index dc5f744..7716120 100644 --- a/src/mainboard/google/nyan/pmic.c +++ b/src/mainboard/google/nyan/pmic.c @@ -59,7 +59,7 @@ static struct as3722_init_reg init_list[] = { {AS3722_LDO11, 0x00, 1}, };
-static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) +static void pmic_write_reg(unsigned bus, u8 reg, u8 val, int do_delay) { if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 4e02365..e0e19a6 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -60,7 +60,7 @@ enum { /* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ static void configure_l2ctlr(void) { - uint32_t val; + u32 val;
val = read_l2ctlr(); val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); @@ -72,7 +72,7 @@ static void configure_l2ctlr(void) /* Configures L2 Auxiliary Control Register for Cortex A15. */ static void configure_l2actlr(void) { - uint32_t val; + u32 val;
val = read_l2actlr(); val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | @@ -151,7 +151,7 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); + u64 romstage_start_time = timestamp_get(); #endif
configure_l2ctlr(); diff --git a/src/mainboard/google/nyan/sdram_configs.c b/src/mainboard/google/nyan/sdram_configs.c index 3b774b2..a700957 100644 --- a/src/mainboard/google/nyan/sdram_configs.c +++ b/src/mainboard/google/nyan/sdram_configs.c @@ -42,7 +42,7 @@ static struct sdram_params sdram_configs[] = {
const struct sdram_params *get_sdram_config() { - uint32_t ramcode = sdram_get_ram_code(); + u32 ramcode = sdram_get_ram_code(); /* * If we need to apply some special hacks to RAMCODE mapping (ex, by * board_id), do that now. diff --git a/src/mainboard/google/nyan_big/boardid.c b/src/mainboard/google/nyan_big/boardid.c index 23b1c6a..f1a1b1a 100644 --- a/src/mainboard/google/nyan_big/boardid.c +++ b/src/mainboard/google/nyan_big/boardid.c @@ -23,7 +23,7 @@
#include "boardid.h"
-uint8_t board_id(void) +u8 board_id(void) { static int id = -1;
diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 298fd6a..9fff2e1 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -82,7 +82,7 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void) { - uint32_t ec_events; + u32 ec_events;
/* The GPIO is active low. */ if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index ff147e2..232c791 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -96,7 +96,7 @@ static void setup_pinmux(void)
// TODO(hungte) Revice pinmux setup, make nice little SoC functions for // every single logical thing instead of dumping a wall of code below. - uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, + u32 pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE, pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
diff --git a/src/mainboard/google/nyan_big/pmic.c b/src/mainboard/google/nyan_big/pmic.c index 4d52f70..3fcab90 100644 --- a/src/mainboard/google/nyan_big/pmic.c +++ b/src/mainboard/google/nyan_big/pmic.c @@ -59,7 +59,7 @@ static struct as3722_init_reg init_list[] = { {AS3722_LDO11, 0x00, 1}, };
-static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) +static void pmic_write_reg(unsigned bus, u8 reg, u8 val, int do_delay) { if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 4e02365..e0e19a6 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -60,7 +60,7 @@ enum { /* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ static void configure_l2ctlr(void) { - uint32_t val; + u32 val;
val = read_l2ctlr(); val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); @@ -72,7 +72,7 @@ static void configure_l2ctlr(void) /* Configures L2 Auxiliary Control Register for Cortex A15. */ static void configure_l2actlr(void) { - uint32_t val; + u32 val;
val = read_l2actlr(); val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | @@ -151,7 +151,7 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); + u64 romstage_start_time = timestamp_get(); #endif
configure_l2ctlr(); diff --git a/src/mainboard/google/nyan_big/sdram_configs.c b/src/mainboard/google/nyan_big/sdram_configs.c index 2aaace4..03c920b 100644 --- a/src/mainboard/google/nyan_big/sdram_configs.c +++ b/src/mainboard/google/nyan_big/sdram_configs.c @@ -46,7 +46,7 @@ static struct sdram_params sdram_configs[] = {
const struct sdram_params *get_sdram_config() { - uint32_t ramcode = sdram_get_ram_code(); + u32 ramcode = sdram_get_ram_code(); /* * If we need to apply some special hacks to RAMCODE mapping (ex, by * board_id), do that now. diff --git a/src/mainboard/google/nyan_blaze/boardid.c b/src/mainboard/google/nyan_blaze/boardid.c index 23b1c6a..f1a1b1a 100644 --- a/src/mainboard/google/nyan_blaze/boardid.c +++ b/src/mainboard/google/nyan_blaze/boardid.c @@ -23,7 +23,7 @@
#include "boardid.h"
-uint8_t board_id(void) +u8 board_id(void) { static int id = -1;
diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 16f0c98..7993b36 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -86,7 +86,7 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void) { - uint32_t ec_events; + u32 ec_events;
/* The GPIO is active low. */ if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO diff --git a/src/mainboard/google/nyan_blaze/mainboard.c b/src/mainboard/google/nyan_blaze/mainboard.c index 8d4f553..ee5f511 100644 --- a/src/mainboard/google/nyan_blaze/mainboard.c +++ b/src/mainboard/google/nyan_blaze/mainboard.c @@ -96,7 +96,7 @@ static void setup_pinmux(void)
// TODO(hungte) Revice pinmux setup, make nice little SoC functions for // every single logical thing instead of dumping a wall of code below. - uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, + u32 pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE, pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
diff --git a/src/mainboard/google/nyan_blaze/pmic.c b/src/mainboard/google/nyan_blaze/pmic.c index 4d52f70..3fcab90 100644 --- a/src/mainboard/google/nyan_blaze/pmic.c +++ b/src/mainboard/google/nyan_blaze/pmic.c @@ -59,7 +59,7 @@ static struct as3722_init_reg init_list[] = { {AS3722_LDO11, 0x00, 1}, };
-static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay) +static void pmic_write_reg(unsigned bus, u8 reg, u8 val, int do_delay) { if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) { printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n", diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..e0e19a6 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -60,7 +60,7 @@ enum { /* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ static void configure_l2ctlr(void) { - uint32_t val; + u32 val;
val = read_l2ctlr(); val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); @@ -72,7 +72,7 @@ static void configure_l2ctlr(void) /* Configures L2 Auxiliary Control Register for Cortex A15. */ static void configure_l2actlr(void) { - uint32_t val; + u32 val;
val = read_l2actlr(); val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | @@ -151,7 +151,7 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); + u64 romstage_start_time = timestamp_get(); #endif
configure_l2ctlr(); diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.c b/src/mainboard/google/nyan_blaze/sdram_configs.c index 74f32fa..2132c90 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.c +++ b/src/mainboard/google/nyan_blaze/sdram_configs.c @@ -42,7 +42,7 @@ static struct sdram_params sdram_configs[] = {
const struct sdram_params *get_sdram_config() { - uint32_t ramcode = sdram_get_ram_code(); + u32 ramcode = sdram_get_ram_code(); /* * If we need to apply some special hacks to RAMCODE mapping (ex, by * board_id), do that now. diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index 7b0807c..5d67b2e 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -84,7 +84,7 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void) { - uint32_t ec_events; + u32 ec_events;
/* The GPIO is active low. */ if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 01d19bc..f04d569 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -378,7 +378,7 @@ enum {
static void tps65090_thru_ec_fet_set(int index) { - uint8_t value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET; + u8 value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET;
if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { printk(BIOS_ERR, diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 248809d..49c3c8b 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -47,8 +47,8 @@ struct pmic_write { int or_orig; // Whether to or in the original value. - uint8_t reg; // Register to write. - uint8_t val; // Value to write. + u8 reg; // Register to write. + u8 val; // Value to write. };
/* @@ -93,8 +93,8 @@ static int setup_power(int is_resume) i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { - uint8_t data = 0; - uint8_t reg = pmic_writes[i].reg; + u8 data = 0; + u8 reg = pmic_writes[i].reg;
if (pmic_writes[i].or_orig) error |= i2c_readb(4, MAX77802_I2C_ADDR, reg, &data); diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 3ab3034..a4e8237 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -97,7 +97,7 @@ int get_recovery_mode_switch(void) int clear_recovery_mode_switch(void) { #if CONFIG_EC_GOOGLE_CHROMEEC - const uint32_t kb_rec_mask = + const u32 kb_rec_mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); /* Unconditionally clear the EC recovery request. */ return google_chromeec_clear_events_b(kb_rec_mask); diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index bd76468..1b4638a 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -52,11 +52,11 @@ int mainboard_io_trap_handler(int smif) return 1; }
-static uint8_t mainboard_smi_ec(void) +static u8 mainboard_smi_ec(void) { - uint8_t cmd = google_chromeec_get_event(); - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt; + u8 cmd = google_chromeec_get_event(); + u16 pmbase = get_pmbase(); + u32 pm1_cnt;
#if CONFIG_ELOG_GSMI /* Log this event */ @@ -80,7 +80,7 @@ static uint8_t mainboard_smi_ec(void)
/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that * this includes the enable bits in the lower 16 bits. */ -void mainboard_smi_gpi(uint32_t alt_gpio_smi) +void mainboard_smi_gpi(u32 alt_gpio_smi) { if (alt_gpio_smi & (1 << EC_SMI_GPI)) { /* Process all pending events */ @@ -88,7 +88,7 @@ void mainboard_smi_gpi(uint32_t alt_gpio_smi) } }
-void mainboard_smi_sleep(uint8_t slp_typ) +void mainboard_smi_sleep(u8 slp_typ) { /* Disable USB charging if required */ switch (slp_typ) { @@ -126,7 +126,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) while (google_chromeec_get_event() != 0); }
-int mainboard_smi_apmc(uint8_t apmc) +int mainboard_smi_apmc(u8 apmc) { switch (apmc) { case APM_CNT_ACPI_ENABLE: diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 7c505e7..54f494a 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -34,7 +34,7 @@ * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz */ -static const uint32_t dual_channel_config = +static const u32 dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
#define SPD_SIZE 256 diff --git a/src/mainboard/google/samus/spd.c b/src/mainboard/google/samus/spd.c index 4371da9..50d86df 100644 --- a/src/mainboard/google/samus/spd.c +++ b/src/mainboard/google/samus/spd.c @@ -27,7 +27,7 @@ #include "gpio.h" #include "spd.h"
-static void mainboard_print_spd_info(uint8_t spd[]) +static void mainboard_print_spd_info(u8 spd[]) { const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index f5e19cd..c33fae4 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -13,9 +13,12 @@ #include <cpu/amd/amdk8_sysconf.h> #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -36,10 +39,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; struct mb_sysconf_t *m = sysconf.mb;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -52,7 +55,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 2b42e73..d0e77bb 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -96,7 +96,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { //first node RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 6c71bad..903fc3d 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -93,7 +93,7 @@ static void *smp_write_config_table(void *v) device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0x64); dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 pci_write_config32(dev, 0x64, dword); @@ -109,7 +109,7 @@ static void *smp_write_config_table(void *v) device_t dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0x64); dword |= (1<<26); pci_write_config32(dev, 0x64, dword); @@ -154,7 +154,7 @@ static void *smp_write_config_table(void *v) device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0x6c); dword |= (1<<4); // enable interrupts printk(BIOS_DEBUG, "6ch: %x\n",dword); diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 9deaaba..0d65623 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -117,7 +117,7 @@ static void setup_early_ipmi_serial()
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 86f2cc6..d313d76 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v) device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0x64); dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7 pci_write_config32(dev, 0x64, dword); @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) device_t dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0x64); dword |= (1<<26); pci_write_config32(dev, 0x64, dword); @@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v) device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0x6c); dword |= (1<<4); // enable interrupts printk(BIOS_DEBUG, "6ch: %x\n",dword); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c index 386d390..0df33a1 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c @@ -42,13 +42,13 @@ static void ec_enter_acpi_mode(void) ec_kbc_write_ib(0xE8); }
-static uint8_t ec_get_smi_event(void) +static u8 ec_get_smi_event(void) { ec_kbc_write_cmd(0x56); return ec_kbc_read_ob(); }
-static void ec_process_smi(uint8_t src) +static void ec_process_smi(u8 src) { /* Reading the SMI source satisfies the EC in terms of responding to * the event, regardless of whether we take an action or not. @@ -66,7 +66,7 @@ static void ec_process_smi(uint8_t src)
static void handle_ec_smi(void) { - uint8_t src; + u8 src;
while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE) ec_process_smi(src); @@ -78,7 +78,7 @@ static void handle_lid_smi(void) outl(ACPI_PM1_CNT_SLEEP(S4), ACPI_PM1_CNT_BLK); }
-int mainboard_smi_apmc(uint8_t data) +int mainboard_smi_apmc(u8 data) { switch (data) { case ACPI_SMI_CMD_ENABLE: @@ -98,7 +98,7 @@ int mainboard_smi_apmc(uint8_t data) return 0; }
-void mainboard_smi_gpi(uint32_t gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GEVENT)) handle_ec_smi(); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index ece65d8..1a6b48f 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -169,8 +169,8 @@ static void rcba_config(void)
static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32;
// program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index ef848fa..1cf90b1 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -52,7 +52,7 @@ void early_mainboard_romstage_entry() * @param fd_mask * @param fd2_mask */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) +void get_func_disables(u32 *fd_mask, u32 *fd2_mask) {
} @@ -66,7 +66,7 @@ void late_mainboard_romstage_entry()
}
-const uint32_t mAzaliaVerbTableData13[] = { +const u32 mAzaliaVerbTableData13[] = { /* *ALC262 Verb Table - 10EC0262 */ @@ -152,7 +152,7 @@ const PCH_AZALIA_VERB_TABLE mAzaliaVerbTable[] = { { 0x000B, /* Number of Rear Jacks = 11 */ 0x0002 /* Number of Front Jacks = 2 */ }, - (uint32_t *)mAzaliaVerbTableData13 } }; + (u32 *)mAzaliaVerbTableData13 } };
const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = { .Pme = 1, diff --git a/src/mainboard/intel/d810e2cb/gpio.c b/src/mainboard/intel/d810e2cb/gpio.c index a95fc9a..fc694e4 100644 --- a/src/mainboard/intel/d810e2cb/gpio.c +++ b/src/mainboard/intel/d810e2cb/gpio.c @@ -25,7 +25,7 @@ static void mb_gpio_init(void) { device_t dev; - uint16_t port; + u16 port;
/* Southbridge GPIOs. */ /* Set the LPC device statically. */ diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 4194a80..f90c1cb 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -101,8 +101,8 @@ static void rcba_config(void)
static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32;
// program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 809feec..0ccde8b 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -64,7 +64,7 @@ static void *smp_write_config_table(void *v) unsigned char bus_chipset, bus_pci; unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; int bus_isa, i; - uint32_t pin, route; + u32 pin, route; device_t dev; struct resource *res; unsigned long rcba; diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c index d8fd04a..9a47767 100644 --- a/src/mainboard/intel/minnowmax/romstage.c +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -40,7 +40,7 @@ void early_mainboard_romstage_entry() * @param fd_mask * @param fd2_mask */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) +void get_func_disables(u32 *fd_mask, u32 *fd2_mask) {
} diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c index b1fb995..69638e0 100644 --- a/src/mainboard/intel/mohonpeak/romstage.c +++ b/src/mainboard/intel/mohonpeak/romstage.c @@ -74,7 +74,7 @@ void late_mainboard_romstage_entry(void) * Get function disables - most of these will be done automatically * @param fd_mask */ -void get_func_disables(uint32_t *mask) +void get_func_disables(u32 *mask) {
} diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index e1c5c80..5a78f2b 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -147,12 +147,12 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink if((sysconf.pci1234[i] & 1) != 1 ) continue; - uint8_t c; + u8 c; if(i<7) { - c = (uint8_t) ('4' + i - 1); + c = (u8) ('4' + i - 1); } else { - c = (uint8_t) ('A' + i - 1 - 6); + c = (u8) ('A' + i - 1 - 6); } printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt current = ALIGN(current, 8); diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c index 4d42f47..cae97e0 100644 --- a/src/mainboard/iwill/dk8_htx/irq_tables.c +++ b/src/mainboard/iwill/dk8_htx/irq_tables.c @@ -13,9 +13,12 @@
#include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -42,9 +45,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum=0; + u8 sum=0; int i;
struct mb_sysconf_t *m; @@ -61,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index a429568..2a8f862 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -67,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index d2371b5..ba46fd5 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -67,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 50869f7..b748c40 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -67,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index cb94337..cd411ac 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -60,13 +60,13 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *Config static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; - uint32_t FcnData; + u32 FcnData; PCIe_SLOT_RESET_INFO *ResetInfo;
- uint32_t GpioMmioAddr; - uint32_t AcpiMmioAddr; - uint8_t Data8; - uint16_t Data16; + u32 GpioMmioAddr; + u32 AcpiMmioAddr; + u8 Data8; + u16 Data16;
FcnData = Data; ResetInfo = ConfigPtr; @@ -77,7 +77,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *Conf WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; - AcpiMmioAddr = (uint32_t)Data16 << 16; + AcpiMmioAddr = (u32)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) @@ -86,7 +86,7 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *Conf switch (ResetInfo->ResetControl) { case AssertSlotReset: Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(uint8_t)BIT6 ; + Data8 &= ~(u8)BIT6 ; Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); Status = AGESA_SUCCESS; break; diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 8d8bbec..673495a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -340,8 +340,8 @@ const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
/* DA Customer table */ -const uint8_t AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = +const u8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = { NBACCESS (MTEnd, 0, 0, 0, 0, 0), /* End of Table */ }; -const uint8_t SizeOfTableON = ARRAY_SIZE(AGESA_MEM_TABLE_ON); +const u8 SizeOfTableON = ARRAY_SIZE(AGESA_MEM_TABLE_ON); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 652d8cb..eac06f7 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -275,8 +275,8 @@ static void rcba_config(void)
static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32;
// program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/mainboard/lenovo/g505s/mainboard_smi.c b/src/mainboard/lenovo/g505s/mainboard_smi.c index 386d390..0df33a1 100644 --- a/src/mainboard/lenovo/g505s/mainboard_smi.c +++ b/src/mainboard/lenovo/g505s/mainboard_smi.c @@ -42,13 +42,13 @@ static void ec_enter_acpi_mode(void) ec_kbc_write_ib(0xE8); }
-static uint8_t ec_get_smi_event(void) +static u8 ec_get_smi_event(void) { ec_kbc_write_cmd(0x56); return ec_kbc_read_ob(); }
-static void ec_process_smi(uint8_t src) +static void ec_process_smi(u8 src) { /* Reading the SMI source satisfies the EC in terms of responding to * the event, regardless of whether we take an action or not. @@ -66,7 +66,7 @@ static void ec_process_smi(uint8_t src)
static void handle_ec_smi(void) { - uint8_t src; + u8 src;
while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE) ec_process_smi(src); @@ -78,7 +78,7 @@ static void handle_lid_smi(void) outl(ACPI_PM1_CNT_SLEEP(S4), ACPI_PM1_CNT_BLK); }
-int mainboard_smi_apmc(uint8_t data) +int mainboard_smi_apmc(u8 data) { switch (data) { case ACPI_SMI_CMD_ENABLE: @@ -98,7 +98,7 @@ int mainboard_smi_apmc(uint8_t data) return 0; }
-void mainboard_smi_gpi(uint32_t gpi_sts) +void mainboard_smi_gpi(u32 gpi_sts) { if (gpi_sts & (1 << EC_SMI_GEVENT)) handle_ec_smi(); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 571a21c..a5cdd85 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -152,8 +152,8 @@ static void rcba_config(void)
static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32;
// program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index af9b1be..4ea920f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -159,8 +159,8 @@ static void rcba_config(void)
static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32;
// program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/mainboard/msi/ms7135/irq_tables.c b/src/mainboard/msi/ms7135/irq_tables.c index f3d1c00..750de8d 100644 --- a/src/mainboard/msi/ms7135/irq_tables.c +++ b/src/mainboard/msi/ms7135/irq_tables.c @@ -41,11 +41,11 @@ extern unsigned char bus_ck804[6]; /** * Add one line to IRQ table. */ -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, + u8 devfn, u8 link0, u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, + u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -71,9 +71,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum = 0; + u8 sum = 0; int i; unsigned sbdn;
@@ -91,7 +91,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *) (addr); + v = (u8 *) (addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/msi/ms7260/irq_tables.c b/src/mainboard/msi/ms7260/irq_tables.c index 15ac432..9b737e8 100644 --- a/src/mainboard/msi/ms7260/irq_tables.c +++ b/src/mainboard/msi/ms7260/irq_tables.c @@ -26,11 +26,11 @@ #include <arch/pirq_routing.h> #include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, - uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, - uint16_t bitmap2, uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, + u8 devfn, u8 link0, u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, + u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -53,8 +53,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned int slot_num, sbdn; - uint8_t *v; - uint8_t sum = 0; + u8 *v; + u8 sum = 0; int i;
/* Will find out all bus num and apic that share with mptable.c @@ -71,7 +71,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c index ea003a8..7da4aa0 100644 --- a/src/mainboard/msi/ms7260/mptable.c +++ b/src/mainboard/msi/ms7260/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0)); if (dev) { diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index fd8fbfb..b900d60 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -78,8 +78,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b); byte |= 0x20; @@ -96,7 +96,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/msi/ms9185/irq_tables.c b/src/mainboard/msi/ms9185/irq_tables.c index 963f5d2..492d6fd 100644 --- a/src/mainboard/msi/ms9185/irq_tables.c +++ b/src/mainboard/msi/ms9185/irq_tables.c @@ -38,9 +38,12 @@ #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -66,9 +69,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum=0; + u8 sum=0; int i;
struct mb_sysconf_t *m; @@ -85,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index b30ab73..09039f9 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -95,7 +95,7 @@ static void *smp_write_config_table(void *v) device_t dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { - uint32_t dword; + u32 dword; dword = pci_read_config32(dev, 0x6c); dword |= (1<<4); // enable interrupts pci_write_config32(dev, 0x6c, dword); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index aabc826..2b37375 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -81,7 +81,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, diff --git a/src/mainboard/msi/ms9282/irq_tables.c b/src/mainboard/msi/ms9282/irq_tables.c index b41ca95..8043d90 100644 --- a/src/mainboard/msi/ms9282/irq_tables.c +++ b/src/mainboard/msi/ms9282/irq_tables.c @@ -37,9 +37,12 @@ #include <cpu/amd/amdk8_sysconf.h> #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -63,11 +66,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; struct mb_sysconf_t *m; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -82,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index 1764cf3..1479059 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 9a6e21f..59b076e 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -87,8 +87,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; @@ -105,7 +105,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // Node 0 RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, diff --git a/src/mainboard/msi/ms9652_fam10/irq_tables.c b/src/mainboard/msi/ms9652_fam10/irq_tables.c index 54a4e54..0e99a0b 100644 --- a/src/mainboard/msi/ms9652_fam10/irq_tables.c +++ b/src/mainboard/msi/ms9652_fam10/irq_tables.c @@ -34,9 +34,12 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,11 +63,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; struct mb_sysconf_t *m; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -79,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 09a25f2..2b251cb 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index b34882e..08346a6 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -67,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 diff --git a/src/mainboard/nvidia/l1_2pvv/irq_tables.c b/src/mainboard/nvidia/l1_2pvv/irq_tables.c index 1629638..6ee0c52 100644 --- a/src/mainboard/nvidia/l1_2pvv/irq_tables.c +++ b/src/mainboard/nvidia/l1_2pvv/irq_tables.c @@ -34,9 +34,12 @@ #include <cpu/amd/amdk8_sysconf.h> #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,11 +63,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; struct mb_sysconf_t *m; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -79,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index e991efd..b82bc67 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index df78a0c..17e66cd 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; @@ -95,7 +95,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c index 0527b68..b1ebb0f 100644 --- a/src/mainboard/rca/rm4100/gpio.c +++ b/src/mainboard/rca/rm4100/gpio.c @@ -26,8 +26,8 @@ static void mb_gpio_init(void) { device_t dev; - uint16_t port; - uint32_t set_gpio; + u16 port; + u32 set_gpio;
/* Southbridge GPIOs. */ /* Set the LPC device statically. */ diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e8ada36..533975c 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -190,8 +190,8 @@ static void rcba_config(void)
static void early_ich7_init(void) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32;
// program secondary mlt XXX byte? pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/mainboard/roda/rk9/ti_pci7xx1.c b/src/mainboard/roda/rk9/ti_pci7xx1.c index f1af9f6..12e76f5 100644 --- a/src/mainboard/roda/rk9/ti_pci7xx1.c +++ b/src/mainboard/roda/rk9/ti_pci7xx1.c @@ -28,7 +28,7 @@ static void pci7xx1_enable(struct device *const dev) { printk(BIOS_DEBUG, "%s: TI PCI7xx1 media controller\n", __func__); if (PCI_FUNC(dev->path.pci.devfn) == 0) { - const uint16_t secondary = dev->bus->secondary; + const u16 secondary = dev->bus->secondary; const unsigned slot = PCI_SLOT(dev->path.pci.devfn);
int fn; diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 5b8646a..86c2857 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -149,7 +149,7 @@ void main(unsigned long bist) }, };
- typedef const uint8_t spd_blob[256]; + typedef const u8 spd_blob[256]; spd_blob *spd_data; size_t spd_file_len;
diff --git a/src/mainboard/sunw/ultra40/irq_tables.c b/src/mainboard/sunw/ultra40/irq_tables.c index a0e21e4..55ed828 100644 --- a/src/mainboard/sunw/ultra40/irq_tables.c +++ b/src/mainboard/sunw/ultra40/irq_tables.c @@ -11,9 +11,12 @@ #include <arch/pirq_routing.h> #include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,9 +63,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -75,7 +78,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index 1ba1dcf..ca91ab8 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 7c112da..552781c 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -69,8 +69,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void sio_setup(void) { unsigned value; - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
@@ -91,7 +91,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/supermicro/h8dme/irq_tables.c b/src/mainboard/supermicro/h8dme/irq_tables.c index 31a9377..1cbb244 100644 --- a/src/mainboard/supermicro/h8dme/irq_tables.c +++ b/src/mainboard/supermicro/h8dme/irq_tables.c @@ -33,9 +33,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -61,10 +64,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -78,7 +81,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index 17067ed..0210231 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -53,7 +53,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index e3e7386..4744f7d 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ @@ -107,7 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) don't know how to switch the SMBus to decode the CPU0 SPDs. So, The memory on each CPU must be an exact match. */ - static const uint16_t spd_addr[] = { + static const u16 spd_addr[] = { // Node 0 RC0 | DIMM0, RC0 | DIMM2, RC0 | DIMM4, RC0 | DIMM6, diff --git a/src/mainboard/supermicro/h8dmr/irq_tables.c b/src/mainboard/supermicro/h8dmr/irq_tables.c index 31a9377..1cbb244 100644 --- a/src/mainboard/supermicro/h8dmr/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr/irq_tables.c @@ -33,9 +33,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -61,10 +64,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -78,7 +81,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index 11db23f..c9c37ef 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -53,7 +53,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 7d1f834..d366d34 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -69,8 +69,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ @@ -91,7 +91,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c index 54a4e54..0e99a0b 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c @@ -34,9 +34,12 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,11 +63,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; struct mb_sysconf_t *m; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -79,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index 4e2d48c..af4df41 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index b393c34..5a58f9a 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -70,8 +70,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c index 0b58879..6098e3b 100644 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c @@ -34,9 +34,12 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,11 +63,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; struct mb_sysconf_t *m; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -79,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 4fbb4c8..eb31484 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 24ecb5d..10209e2 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -76,8 +76,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte; enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 3423e51..52a3f00 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -84,7 +84,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the LDN the register belongs to, before you can access the register. */ -static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8712f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); diff --git a/src/mainboard/technexion/tim5690/speaker.c b/src/mainboard/technexion/tim5690/speaker.c index e4d2a87..93649ef 100644 --- a/src/mainboard/technexion/tim5690/speaker.c +++ b/src/mainboard/technexion/tim5690/speaker.c @@ -36,7 +36,7 @@
#include "speaker.h"
-void speaker_init(uint8_t time) { +void speaker_init(u8 time) { /* SB600 RRG. * Options_0 - RW - 8 bits - [PM_Reg: 60h]. * SpkrEn, bit[5]=1b, Setting this bit will configure GPIO2 to be speaker output. diff --git a/src/mainboard/technexion/tim5690/tn_post_code.c b/src/mainboard/technexion/tim5690/tn_post_code.c index 422627e..c0af144 100644 --- a/src/mainboard/technexion/tim5690/tn_post_code.c +++ b/src/mainboard/technexion/tim5690/tn_post_code.c @@ -39,7 +39,7 @@ // TechNexion's Post Code Initially. void technexion_post_code_init(void) { - uint8_t reg8_data; + u8 reg8_data; device_t dev=0;
// SMBus Module and ACPI Block (Device 20, Function 0) @@ -130,9 +130,9 @@ void technexion_post_code_init(void)
/* TechNexion's Post Code. */ -void technexion_post_code(uint8_t udata8) +void technexion_post_code(u8 udata8) { - uint8_t u8_data; + u8 u8_data; device_t dev=0;
// SMBus Module and ACPI Block (Device 20, Function 0) diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c index bcb02bc..dbc3950 100644 --- a/src/mainboard/thomson/ip1000/gpio.c +++ b/src/mainboard/thomson/ip1000/gpio.c @@ -26,8 +26,8 @@ static void mb_gpio_init(void) { device_t dev; - uint16_t port; - uint32_t set_gpio; + u16 port; + u32 set_gpio;
/* Southbridge GPIOs. */ /* Set the LPC device statically. */ diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 2b22227..2743aa8 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -29,17 +29,17 @@ void bootblock_mainboard_init(void) void *uart_clock_ctrl = NULL;
/* Enable the GPIO module */ - writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac)); + writel((0x2 << 0) | (1 << 18), (u32 *)(0x44e00000 + 0xac));
/* Disable interrupts from these GPIOs */ - setbits_le32((uint32_t *)(0x4804c000 + 0x3c), 0xf << 21); + setbits_le32((u32 *)(0x4804c000 + 0x3c), 0xf << 21);
/* Enable output */ - clrbits_le32((uint32_t *)(0x4804c000 + 0x134), 0xf << 21); + clrbits_le32((u32 *)(0x4804c000 + 0x134), 0xf << 21);
/* Set every other light */ - clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); - setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + clrbits_le32((u32 *)(0x4804c000 + 0x13c), 0xf << 21); + setbits_le32((u32 *)(0x4804c000 + 0x13c), 0x5 << 21);
/* Set up the UART we're going to use */ if (CONFIG_UART_FOR_CONSOLE == 0) { diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 371d9a3..b5e2c9e 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -18,7 +18,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; + u32 config_map; unsigned dst_node; unsigned dst_link; unsigned bus_base; diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 90299a7..d2d3112 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -18,7 +18,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; + u32 config_map; unsigned dst_node; unsigned dst_link; unsigned bus_base; diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 32fc639..a032ac2 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -18,7 +18,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; + u32 config_map; unsigned dst_node; unsigned dst_link; unsigned bus_base; diff --git a/src/mainboard/tyan/s2881/irq_tables.c b/src/mainboard/tyan/s2881/irq_tables.c index 53e761d..55076d5 100644 --- a/src/mainboard/tyan/s2881/irq_tables.c +++ b/src/mainboard/tyan/s2881/irq_tables.c @@ -12,9 +12,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -46,9 +49,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -61,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index c020f3e..bf93cd7 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -56,7 +56,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c index 218ddce..45add1f 100644 --- a/src/mainboard/tyan/s2882/irq_tables.c +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -52,7 +52,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; + u32 config_map; unsigned dst_node; unsigned dst_link; unsigned bus_base; @@ -76,9 +76,12 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; }
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -100,9 +103,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum=0; + u8 sum=0; int i;
unsigned char bus_chain_0; @@ -161,7 +164,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...\n", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index 6c07965..b751400 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -19,7 +19,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; + u32 config_map; unsigned dst_node; unsigned dst_link; unsigned bus_base; diff --git a/src/mainboard/tyan/s2885/irq_tables.c b/src/mainboard/tyan/s2885/irq_tables.c index f217365..b7a0368 100644 --- a/src/mainboard/tyan/s2885/irq_tables.c +++ b/src/mainboard/tyan/s2885/irq_tables.c @@ -12,9 +12,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -49,9 +52,9 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -64,7 +67,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index df602ea..be64597 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -56,7 +56,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 diff --git a/src/mainboard/tyan/s2891/irq_tables.c b/src/mainboard/tyan/s2891/irq_tables.c index ea180db..4328046 100644 --- a/src/mainboard/tyan/s2891/irq_tables.c +++ b/src/mainboard/tyan/s2891/irq_tables.c @@ -12,9 +12,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -52,10 +55,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -69,7 +72,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index cb49434..5da4e36 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index e97b026..21e44bb 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -44,8 +44,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
/* subject decoding*/ byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); @@ -70,7 +70,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 diff --git a/src/mainboard/tyan/s2892/irq_tables.c b/src/mainboard/tyan/s2892/irq_tables.c index b3f54a4..bcd7d04 100644 --- a/src/mainboard/tyan/s2892/irq_tables.c +++ b/src/mainboard/tyan/s2892/irq_tables.c @@ -12,9 +12,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -50,10 +53,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -67,7 +70,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index 882ac69..377b06e 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 57da072..76525d2 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -51,8 +51,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; @@ -65,7 +65,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 diff --git a/src/mainboard/tyan/s2895/irq_tables.c b/src/mainboard/tyan/s2895/irq_tables.c index a247c3e..06542be 100644 --- a/src/mainboard/tyan/s2895/irq_tables.c +++ b/src/mainboard/tyan/s2895/irq_tables.c @@ -12,9 +12,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -58,10 +61,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -75,7 +78,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index 20fa92c..fabd87c 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/tyan/s2912/irq_tables.c b/src/mainboard/tyan/s2912/irq_tables.c index fd219ad..00204be 100644 --- a/src/mainboard/tyan/s2912/irq_tables.c +++ b/src/mainboard/tyan/s2912/irq_tables.c @@ -34,9 +34,12 @@ #include <cpu/amd/amdk8_sysconf.h> #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,11 +63,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; struct mb_sysconf_t *m; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -79,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index 133ce43..cbe703f 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 55cb95e..e9b9faa 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -77,8 +77,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; @@ -96,7 +96,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, diff --git a/src/mainboard/tyan/s2912_fam10/irq_tables.c b/src/mainboard/tyan/s2912_fam10/irq_tables.c index 54a4e54..0e99a0b 100644 --- a/src/mainboard/tyan/s2912_fam10/irq_tables.c +++ b/src/mainboard/tyan/s2912_fam10/irq_tables.c @@ -34,9 +34,12 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h"
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -60,11 +63,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; struct mb_sysconf_t *m; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -79,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index e15387d..64f5cf9 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 6dae693..633ca83 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -78,8 +78,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index dcc0fd8..622dee6 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -18,7 +18,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; + u32 config_map; unsigned dst_node; unsigned dst_link; unsigned bus_base; diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 350b55c..97c50a3 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -18,7 +18,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) return 0; } for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - uint32_t config_map; + u32 config_map; unsigned dst_node; unsigned dst_link; unsigned bus_base; diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 17379b5..54379df 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -73,7 +73,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index c9b1e8b..6c7397c 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -147,7 +147,7 @@ static void enable_mainboard_devices(void) */ static void enable_shadow_ram(void) { - uint8_t shadowreg; + u8 shadowreg;
/* * Changed the value from 0x2a to 0x3f. "read only" may block "write"? diff --git a/src/mainboard/winent/mb6047/irq_tables.c b/src/mainboard/winent/mb6047/irq_tables.c index 6fe7349..1e2717a 100644 --- a/src/mainboard/winent/mb6047/irq_tables.c +++ b/src/mainboard/winent/mb6047/irq_tables.c @@ -12,9 +12,12 @@
#include <cpu/amd/amdk8_sysconf.h>
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, - uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, - uint8_t slot, uint8_t rfu) +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, + u16 bitmap0, + u8 link1, u16 bitmap1, u8 link2, u16 bitmap2,u8 link3, + u16 bitmap3, + u8 slot, u8 rfu) { pirq_info->bus = bus; pirq_info->devfn = devfn; @@ -43,10 +46,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; - uint8_t *v; + u8 *v; unsigned sbdn;
- uint8_t sum=0; + u8 sum=0; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c @@ -60,7 +63,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr); - v = (uint8_t *)(addr); + v = (u8 *)(addr);
pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index 26e79ca..e4989cb 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - uint32_t dword; + u32 dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index a725beb..161fbf7 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -46,8 +46,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte;
/* subject decoding*/ byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); @@ -64,7 +64,7 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 2b2dad5..a149bdd 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -41,7 +41,7 @@ #include <Options.h> #include "amdfam10.h"
-extern uint32_t agesawrapper_amdinitmid(void); +extern u32 agesawrapper_amdinitmid(void);
typedef struct amdfam10_sysconf_t sys_info_conf_t; typedef struct dram_base_mask { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index fe9cd72..c8e4db5 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -456,8 +456,8 @@ static void set_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; + u32 topmem = (u32) bsp_topmem(); + u32 sys_mem;
/* refer to UMA Size Consideration in Family12h BKDG. */ /* Please reference MemNGetUmaSizeLN () */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index ff669ef..1a10216 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -526,8 +526,8 @@ static void domain_read_resources(device_t dev) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; + u32 topmem = (u32) bsp_topmem(); + u32 sys_mem;
/* refer to UMA Size Consideration in Family14h BKDG. */ sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c030d57..5bb14f7 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -763,8 +763,8 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; + u32 topmem = (u32) bsp_topmem(); + u32 sys_mem;
/* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index a27e902..505ce74 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -758,8 +758,8 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; + u32 topmem = (u32) bsp_topmem(); + u32 sys_mem;
/* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ @@ -925,7 +925,7 @@ static void domain_set_resources(struct device *dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + u64 topmem2 = bsp_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c7f7fef..0c88864 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -756,8 +756,8 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; + u32 topmem = (u32) bsp_topmem(); + u32 sys_mem;
/* refer to UMA Size Consideration in Family15h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ @@ -923,7 +923,7 @@ static void domain_set_resources(device_t dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + u64 topmem2 = bsp_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 86adfae..891b62c 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -798,8 +798,8 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; + u32 topmem = (u32) bsp_topmem(); + u32 sys_mem;
/* refer to UMA Size Consideration in Family16h BKDG. */ /* Please reference MemNGetUmaSizeOR () */ @@ -967,7 +967,7 @@ static void domain_set_resources(device_t dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + u64 topmem2 = bsp_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index 463fb7c..b838d33 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -68,7 +68,7 @@ unsigned long acpi_create_srat_lapics(unsigned long current) return current; }
-static unsigned long resk(uint64_t value) +static unsigned long resk(u64 value) { unsigned long resultk; if (value < (1ULL << 42)) { diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a8a8155..ee720af 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -833,7 +833,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); + u32 topmem = (u32) bsp_topmem(); /* refer to UMA Size Consideration in 780 BDG. */ switch (topmem) { case 0x10000000: /* 256M system memory */ diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c index 3f3b009..e30ec25 100644 --- a/src/northbridge/amd/amdk8/acpi.c +++ b/src/northbridge/amd/amdk8/acpi.c @@ -74,7 +74,7 @@ unsigned long acpi_create_srat_lapics(unsigned long current) return current; }
-static unsigned long resk(uint64_t value) +static unsigned long resk(u64 value) { unsigned long resultk; if (value < (1ULL << 42)) { @@ -233,7 +233,7 @@ static void k8acpi_write_HT(void) {
static void k8acpi_write_pci_data(int dlen, const char *name, int offset) { device_t dev; - uint32_t dword; + u32 dword; int i;
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 8abb31f..880e3cc 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -113,7 +113,7 @@ #endif
-static inline void print_linkn (const char *strval, uint8_t byteval) +static inline void print_linkn (const char *strval, u8 byteval) { printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); } @@ -246,7 +246,7 @@ static int link_connection(u8 src, u8 dest)
static void rename_temp_node(u8 node) { - uint32_t val; + u32 val;
print_spew("Renaming current temporary node to "); print_spew_hex8(node); @@ -275,11 +275,11 @@ static int verify_connection(u8 dest) return 1; }
-static uint16_t read_freq_cap(device_t dev, uint8_t pos) +static u16 read_freq_cap(device_t dev, u8 pos) { /* Handle bugs in valid hypertransport frequency reporting */ - uint16_t freq_cap; - uint32_t id; + u16 freq_cap; + u32 id;
freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ @@ -303,13 +303,14 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) return freq_cap; }
-static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2) +static int optimize_connection(device_t node1, u8 link1, device_t node2, + u8 link2) { - static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; - static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; - uint16_t freq_cap1, freq_cap2; - uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2; - uint8_t freq, old_freq; + static const u8 link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; + static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; + u16 freq_cap1, freq_cap2; + u8 width_cap1, width_cap2, width, old_width, ln_width1, ln_width2; + u8 freq, old_freq; int needs_reset; /* Set link width and frequency */
@@ -376,7 +377,7 @@ static int optimize_connection(device_t node1, uint8_t link1, device_t node2, ui return needs_reset; }
-static uint8_t get_linkn_first(uint8_t byte) +static u8 get_linkn_first(u8 byte) { if(byte & 0x02) { byte = 0; } else if(byte & 0x04) { byte = 1; } @@ -385,7 +386,7 @@ static uint8_t get_linkn_first(uint8_t byte) }
#if TRY_HIGH_FIRST == 1 -static uint8_t get_linkn_last(uint8_t byte) +static u8 get_linkn_last(u8 byte) { if(byte & 0x02) { byte &= 0x0f; byte |= 0x00; } if(byte & 0x04) { byte &= 0x0f; byte |= 0x10; } @@ -395,7 +396,7 @@ static uint8_t get_linkn_last(uint8_t byte) #endif
#if (CONFIG_MAX_PHYSICAL_CPUS > 2) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED -static uint8_t get_linkn_last_count(uint8_t byte) +static u8 get_linkn_last_count(u8 byte) { byte &= 0x0f; if(byte & 0x02) { byte &= 0xcf; byte |= 0x00; byte+=0x40; } @@ -407,12 +408,12 @@ static uint8_t get_linkn_last_count(uint8_t byte)
static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is for temp use*/ { - uint8_t linkn; - uint32_t val; + u8 linkn; + u32 val; val = 1; for(linkn = 0; linkn<3; linkn++) { - uint8_t regpos; - uint32_t reg; + u8 regpos; + u32 reg; regpos = 0x98 + 0x20 * linkn; reg = pci_read_config32(NODE_HT(source), regpos); if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/ @@ -425,8 +426,8 @@ static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is fo
static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) { - uint32_t val; - uint32_t val_s; + u32 val; + u32 val_s; val = 1<<(linkn+1); val |= 1<<(linkn+1+8); /*for direct connect response route should equal to request table*/
@@ -452,7 +453,7 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn) #if CROSS_BAR_47_56 static void opt_broadcast_rt(u8 source, u8 dest, u8 kickout) { - uint32_t val; + u32 val; val = get_row(source, dest); val -= link_connection(source, kickout)<<16; fill_row(source, dest, val); @@ -469,7 +470,7 @@ static void opt_broadcast_rt_group(const u8 *conn, int num)
static void opt_broadcast_rt_plus(u8 source, u8 dest, u8 kickout) { - uint32_t val; + u32 val; val = get_row(source, dest); val += link_connection(source, kickout)<<16; fill_row(source, dest, val); @@ -503,7 +504,7 @@ static void setup_temp_row(u8 source, u8 dest)
static void setup_remote_node(u8 node) { - static const uint8_t pci_reg[] = { + static const u8 pci_reg[] = { 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78, 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, @@ -518,8 +519,8 @@ static void setup_remote_node(u8 node)
/* copy the default resource map from node 0 */ for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { - uint32_t value; - uint8_t reg; + u32 value; + u8 reg; reg = pci_reg[i]; value = pci_read_config32(NODE_MP(0), reg); pci_write_config32(NODE_MP(7), reg, value); @@ -539,8 +540,8 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif #endif { /*for indirect connection, we need to compute the val from val_s(source, source), and val_g(source, gateway) */ - uint32_t val_s; - uint32_t val; + u32 val_s; + u32 val; #if !CROSS_BAR_47_56 u8 gateway; u8 diff; @@ -564,7 +565,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif if(diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/ val_s -= val & 0xff; #if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED - uint8_t byte; + u8 byte; /* Some node have two links left * don't worry we only have (2, (3 as source need to handle */ @@ -691,7 +692,7 @@ static unsigned setup_smp2(void) { unsigned nodes; u8 byte; - uint32_t val; + u32 val; nodes = 2;
setup_row_local(0, 0); /* it will update the broadcast RT*/ @@ -767,7 +768,7 @@ static unsigned setup_smp4(void) { unsigned nodes; u8 byte; - uint32_t val; + u32 val;
nodes=4;
@@ -938,7 +939,7 @@ static unsigned setup_smp6(void) { unsigned nodes; u8 byte; - uint32_t val; + u32 val;
nodes=6;
@@ -1141,7 +1142,7 @@ static unsigned setup_smp8(void) { unsigned nodes; u8 byte; - uint32_t val; + u32 val;
nodes=8;
@@ -1565,7 +1566,7 @@ static void clear_dead_routes(unsigned nodes)
/* Update the local row */ for( node=0; node<nodes; node++) { - uint32_t val = 0; + u32 val = 0; for(row =0; row<nodes; row++) { val |= get_row(node, row); } @@ -1619,7 +1620,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif for (node = 0; node < nodes; node++) { device_t dev; - uint32_t val; + u32 val; dev = NODE_HT(node);
/* Set the Total CPU and Node count in the system */ @@ -1663,7 +1664,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) int needs_reset = 0; for(node = 0; node < nodes; node++) { device_t dev; - uint32_t cmd; + u32 cmd; dev = NODE_MC(node); #if !CONFIG_K8_REV_F_SUPPORT if (is_cpu_pre_c0()) { @@ -1695,7 +1696,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
} else if (is_cpu_pre_d0()) { // d0 later don't need it - uint32_t cmd_ref; + u32 cmd_ref; /* Errata 98 * Set Clk Ramp Hystersis to 7 * Clock Power/Timing Low @@ -1733,13 +1734,13 @@ static int optimize_link_read_pointers(unsigned nodes) int needs_reset = 0; for(node = 0; node < nodes; node++) { device_t f0_dev, f3_dev; - uint32_t cmd_ref, cmd; + u32 cmd_ref, cmd; int link; f0_dev = NODE_HT(node); f3_dev = NODE_MC(node); cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc); for(link = 0; link < 3; link++) { - uint32_t link_type; + u32 link_type; unsigned reg; /* This works on an Athlon64 because unimplemented links return 0 */ reg = 0x98 + (link * 0x20); @@ -1794,7 +1795,7 @@ static int optimize_link_coherent_ht(void)
#if CONFIG_MAX_PHYSICAL_CPUS > 4 if(nodes>4) { - static const uint8_t opt_conn6[] ={ + static const u8 opt_conn6[] ={ 2, 4, 3, 5, #if !CROSS_BAR_47_56 @@ -1807,7 +1808,7 @@ static int optimize_link_coherent_ht(void)
#if CONFIG_MAX_PHYSICAL_CPUS > 6 if(nodes>6) { - static const uint8_t opt_conn8[] ={ + static const u8 opt_conn8[] ={ 4, 6, #if CROSS_BAR_47_56 4, 7, diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 4f9d8ca..8613303 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -22,7 +22,7 @@ static inline void print_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -32,7 +32,7 @@ static inline void print_pci_devices(void) print_debug_pci_dev(dev); printk(BIOS_DEBUG, " %04x:%04x\n", (id & 0xffff), (id>>16)); if(((dev>>12) & 0x07) == 0) { - uint8_t hdr_type; + u8 hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); if((hdr_type & 0x80) != 0x80) { dev += PCI_DEV(0,0,7); @@ -58,15 +58,16 @@ static void dump_pci_device(unsigned dev) }
#if CONFIG_K8_REV_F_SUPPORT -static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); -static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) +static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, + u32 index); +static inline void dump_pci_device_index_wait(unsigned dev, u32 index_reg) { int i; print_debug_pci_dev(dev); print_debug(" -- index_reg="); print_debug_hex32(index_reg);
for(i = 0; i < 0x40; i++) { - uint32_t val; + u32 val; int j; printk(BIOS_DEBUG, "\n%02x:",i); val = pci_read_config32_index_wait(dev, index_reg, i); @@ -86,7 +87,7 @@ static inline void dump_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -96,7 +97,7 @@ static inline void dump_pci_devices(void) dump_pci_device(dev);
if(((dev>>12) & 0x07) == 0) { - uint8_t hdr_type; + u8 hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); if((hdr_type & 0x80) != 0x80) { dev += PCI_DEV(0,0,7); @@ -111,7 +112,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn) for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -121,7 +122,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn) dump_pci_device(dev);
if(((dev>>12) & 0x07) == 0) { - uint8_t hdr_type; + u8 hdr_type; hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); if((hdr_type & 0x80) != 0x80) { dev += PCI_DEV(0,0,7); @@ -211,7 +212,7 @@ static inline void dump_io_resources(unsigned port) udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); for(i=0;i<256;i++) { - uint8_t val; + u8 val; if ((i & 0x0f) == 0) { printk(BIOS_DEBUG, "%02x:", i); } diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6449f4b..d9cd961 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -17,16 +17,16 @@ static void enumerate_ht_chain(void) #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid = 0; - uint8_t real_last_pos = 0; + u8 real_last_pos = 0; int ht_dev_num = 0; // except host_bridge - uint8_t end_used = 0; + u8 end_used = 0; #endif
dev = PCI_DEV(0,0,0); next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; do { - uint32_t id; - uint8_t hdr_type, pos; + u32 id; + u8 hdr_type, pos; last_unitid = next_unitid;
id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -48,10 +48,10 @@ static void enumerate_ht_chain(void) pos = pci_read_config8(dev, PCI_CAPABILITY_LIST); } while(pos != 0) { - uint8_t cap; + u8 cap; cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); if (cap == PCI_CAP_ID_HT) { - uint16_t flags; + u16 flags; /* Read and write and reread flags so the link * direction bit is valid. */ @@ -128,7 +128,7 @@ out:
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { - uint16_t flags; + u16 flags; dev = PCI_DEV(0,real_last_unitid, 0); flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c index d89dadc..90b7b0d 100644 --- a/src/northbridge/amd/amdk8/f_pci.c +++ b/src/northbridge/amd/amdk8/f_pci.c @@ -3,9 +3,9 @@
#ifdef UNUSED_CODE /* bit [10,8] are dev func, bit[1,0] are dev index */ -static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index) +static u32 pci_read_config32_index(device_t dev, u32 index_reg, u32 index) { - uint32_t dword; + u32 dword;
pci_write_config32(dev, index_reg, index);
@@ -14,7 +14,8 @@ static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32 return dword; }
-static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +static void pci_write_config32_index(device_t dev, u32 index_reg, u32 index, + u32 data) { pci_write_config32(dev, index_reg, index);
@@ -22,9 +23,10 @@ static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t } #endif
-static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index) +static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, + u32 index) { - uint32_t dword; + u32 dword;
index &= ~(1<<30); pci_write_config32(dev, index_reg, index); @@ -38,9 +40,10 @@ static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, u return dword; }
-static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +static void pci_write_config32_index_wait(device_t dev, u32 index_reg, + u32 index, u32 data) { - uint32_t dword; + u32 dword;
pci_write_config32(dev, index_reg + 0x4, data);
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 2db726c..b90506e 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -186,7 +186,7 @@ void get_sblk_pci1234(void)
device_t dev; int i,j; - uint32_t dword; + u32 dword;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); @@ -216,7 +216,7 @@ void get_sblk_pci1234(void) dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(j=0;j<4;j++) { - uint32_t dwordx; + u32 dwordx; dwordx = pci_read_config32(dev, 0xe0 + j*4); dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */ if((dwordx & 0xff1) == dword) { /* SBLINK */ diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index cf8ad52..e8a667d 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -13,15 +13,15 @@ #define K8_ALLOCATE_MMIO_RANGE 0 #endif
-static inline void print_linkn_in (const char *strval, uint8_t byteval) +static inline void print_linkn_in (const char *strval, u8 byteval) { printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); }
-static uint8_t ht_lookup_capability(device_t dev, uint16_t val) +static u8 ht_lookup_capability(device_t dev, u16 val) { - uint8_t pos; - uint8_t hdr_type; + u8 pos; + u8 hdr_type;
hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); pos = 0; @@ -35,10 +35,10 @@ static uint8_t ht_lookup_capability(device_t dev, uint16_t val) pos = pci_read_config8(dev, pos); } while(pos != 0) { /* loop through the linked list */ - uint8_t cap; + u8 cap; cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); if (cap == PCI_CAP_ID_HT) { - uint16_t flags; + u16 flags;
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); if ((flags >> 13) == val) { @@ -51,7 +51,7 @@ static uint8_t ht_lookup_capability(device_t dev, uint16_t val) return pos; }
-static uint8_t ht_lookup_slave_capability(device_t dev) +static u8 ht_lookup_slave_capability(device_t dev) { return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format } @@ -63,7 +63,7 @@ static uint8_t ht_lookup_host_capability(device_t dev) } #endif
-static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid) +static void ht_collapse_previous_enumeration(u8 bus, unsigned offset_unitid) { device_t dev;
@@ -76,7 +76,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid
/* Check if is already collapsed */ if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) { - uint32_t id; + u32 id; dev = PCI_DEV(bus, 0, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); if (!((id == 0xffffffff) || (id == 0x00000000) || @@ -89,9 +89,9 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid * hypertransport enumeration. */ for(dev = PCI_DEV(bus, 1, 0); dev <= PCI_DEV(bus, 0x1f, 0x7); dev += PCI_DEV(0, 1, 0)) { - uint32_t id; - uint8_t pos; - uint16_t flags; + u32 id; + u8 pos; + u16 flags;
id = pci_read_config32(dev, PCI_VENDOR_ID); if ((id == 0xffffffff) || (id == 0x00000000) || @@ -111,11 +111,11 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid } }
-static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) +static u16 ht_read_freq_cap(device_t dev, u8 pos) { /* Handle bugs in valid hypertransport frequency reporting */ - uint16_t freq_cap; - uint32_t id; + u16 freq_cap; + u32 id;
freq_cap = pci_read_config16(dev, pos); printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap); @@ -157,11 +157,11 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) return freq_cap; }
-static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) +static u8 ht_read_width_cap(device_t dev, u8 pos) { - uint8_t width_cap = pci_read_config8(dev, pos); + u8 width_cap = pci_read_config8(dev, pos);
- uint32_t id; + u32 id;
id = pci_read_config32(dev, 0);
@@ -203,14 +203,14 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) PCI_HT_CAP_SLAVE_FREQ_CAP1)
static int ht_optimize_link( - device_t dev1, uint8_t pos1, unsigned offs1, - device_t dev2, uint8_t pos2, unsigned offs2) + device_t dev1, u8 pos1, unsigned offs1, + device_t dev2, u8 pos2, unsigned offs2) { - static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; - static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; - uint16_t freq_cap1, freq_cap2; - uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2; - uint8_t freq, old_freq; + static const u8 link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; + static const u8 pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; + u16 freq_cap1, freq_cap2; + u8 width_cap1, width_cap2, width, old_width, ln_width1, ln_width2; + u8 freq, old_freq; int needs_reset; /* Set link width and frequency */
@@ -290,14 +290,15 @@ static int ht_optimize_link( }
#if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo) +static void ht_setup_chainx(device_t udev, u8 upos, u8 bus, + unsigned offset_unitid, struct sys_info *sysinfo) #else static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) #endif { //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
- uint8_t next_unitid, last_unitid; + u8 next_unitid, last_unitid; unsigned uoffs;
#if !CONFIG_RAMINIT_SYSINFO @@ -307,19 +308,19 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid = 0; - uint8_t real_last_pos = 0; + u8 real_last_pos = 0; int ht_dev_num = 0; - uint8_t end_used = 0; + u8 end_used = 0; #endif
uoffs = PCI_HT_HOST_OFFS; next_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
do { - uint32_t id; - uint8_t pos; - uint16_t flags, ctrl; - uint8_t count; + u32 id; + u8 pos; + u16 flags, ctrl; + u8 count; unsigned offs;
/* Wait until the link initialization is complete */ @@ -437,7 +438,7 @@ end_of_chain: ;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { - uint16_t flags; + u16 flags; flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; @@ -501,10 +502,10 @@ static int ht_setup_chain(device_t udev, unsigned upos) } #endif
-static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val) +static int optimize_link_read_pointer(u8 node, u8 linkn, u8 linkt, u8 val) { - uint32_t dword, dword_old; - uint8_t link_type; + u32 dword, dword_old; + u8 link_type;
/* This works on an Athlon64 because unimplemented links return 0 */ dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20)); @@ -525,18 +526,18 @@ static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt return 0; }
-static int optimize_link_read_pointers_chain(uint8_t ht_c_num) +static int optimize_link_read_pointers_chain(u8 ht_c_num) { int reset_needed; - uint8_t i; + u8 i;
reset_needed = 0;
for (i = 0; i < ht_c_num; i++) { - uint32_t reg; - uint8_t nodeid, linkn; - uint8_t busn; - uint8_t val; + u32 reg; + u8 nodeid, linkn; + u8 busn; + u8 val; unsigned devn = 1;
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) @@ -569,10 +570,11 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) }
#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55 -static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val) +static int set_ht_link_buffer_count(u8 node, u8 linkn, u8 linkt, + unsigned val) { - uint32_t dword; - uint8_t link_type; + u32 dword; + u8 link_type; unsigned regpos; device_t dev;
@@ -595,17 +597,17 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, return 0; }
-static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val) +static int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val) { int reset_needed; - uint8_t i; + u8 i;
reset_needed = 0;
for (i = 0; i < ht_c_num; i++) { - uint32_t reg; - uint8_t nodeid, linkn; - uint8_t busn; + u32 reg; + u8 nodeid, linkn; + u8 busn; unsigned devn;
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); @@ -629,7 +631,7 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, #endif
#if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo) +static void ht_setup_chains(u8 ht_c_num, struct sys_info *sysinfo) #else static int ht_setup_chains(uint8_t ht_c_num) #endif @@ -639,9 +641,9 @@ static int ht_setup_chains(uint8_t ht_c_num) * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ - uint8_t upos; + u8 upos; device_t udev; - uint8_t i; + u8 i;
#if !CONFIG_RAMINIT_SYSINFO int reset_needed = 0; @@ -651,11 +653,11 @@ static int ht_setup_chains(uint8_t ht_c_num)
// first one is SB Chain for (i = 0; i < ht_c_num; i++) { - uint32_t reg; - uint8_t devpos; + u32 reg; + u8 devpos; unsigned regpos; - uint32_t dword; - uint8_t busn; + u32 dword; + u8 busn; unsigned offset_unitid = 0;
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); @@ -708,12 +710,12 @@ static void ht_setup_chains_x(struct sys_info *sysinfo) static int ht_setup_chains_x(void) #endif { - uint8_t nodeid; - uint32_t reg; - uint32_t tempreg; - uint8_t next_busn; - uint8_t ht_c_num; - uint8_t nodes; + u8 nodeid; + u32 reg; + u32 tempreg; + u8 next_busn; + u8 ht_c_num; + u8 nodes; #if CONFIG_K8_ALLOCATE_IO_RANGE unsigned next_io_base; #endif @@ -756,7 +758,7 @@ static int ht_setup_chains_x(void)
for(nodeid=0; nodeid<nodes; nodeid++) { device_t dev; - uint8_t linkn; + u8 linkn; dev = PCI_DEV(0, 0x18+nodeid,0); for(linkn = 0; linkn<3; linkn++) { unsigned regpos; @@ -822,7 +824,7 @@ static int ht_setup_chains_x(void) }
/* recount ht_c_num*/ - uint8_t i=0; + u8 i=0; for(ht_c_num=0;ht_c_num<4; ht_c_num++) { reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4); if(((reg & 0xf) != 0x0)) { diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index cab56c2..c2ab2fb 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -69,7 +69,7 @@ static void set_agp_aperture(device_t dev) resource = probe_resource(dev, 0x94); if (resource) { device_t pdev; - uint32_t gart_base, gart_acr; + u32 gart_base, gart_acr;
/* Remember this resource has been stored */ resource->flags |= IORESOURCE_STORED; @@ -109,7 +109,7 @@ static void mcf3_set_resources(device_t dev)
static void misc_control_init(struct device *dev) { - uint32_t cmd, cmd_ref; + u32 cmd, cmd_ref; int needs_reset; struct device *f0_dev;
@@ -163,7 +163,7 @@ static void misc_control_init(struct device *dev) } else if(is_cpu_pre_d0()) { struct device *f2_dev; - uint32_t dcl; + u32 dcl; f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2); /* Errata 98 * Set Clk Ramp Hystersis to 7 @@ -187,7 +187,7 @@ static void misc_control_init(struct device *dev) int link; cmd_ref = cmd = pci_read_config32(dev, 0xdc); for(link = 0; link < 3; link++) { - uint32_t link_type; + u32 link_type; unsigned reg; /* This works on an Athlon64 because unimplemented links return 0 */ reg = 0x98 + (link * 0x20); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 081ec6d..72bdd01 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -863,7 +863,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); + u32 topmem = (u32) bsp_topmem();
#if !CONFIG_BOARD_ASROCK_939A785GMH && !CONFIG_BOARD_AMD_MAHOGANY
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 19f83b9..b445bf2 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -542,7 +542,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
static void hw_enable_ecc(const struct mem_controller *ctrl) { - uint32_t dcl, nbcap; + u32 dcl, nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_DimmEccEn; @@ -557,7 +557,7 @@ static void hw_enable_ecc(const struct mem_controller *ctrl)
static int is_dual_channel(const struct mem_controller *ctrl) { - uint32_t dcl; + u32 dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return dcl & DCL_128BitEn; } @@ -571,7 +571,7 @@ static int is_opteron(const struct mem_controller *ctrl) * use dual channel, so if we really check for opteron here, we * need to fix up all code using this function, too. */ - uint32_t nbcap; + u32 nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit); } @@ -582,7 +582,7 @@ static int is_registered(const struct mem_controller *ctrl) * If we are not registered we are unbuffered. * This function must be called after spd_handle_unbuffered_dimms. */ - uint32_t dcl; + u32 dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return !(dcl & DCL_UnBuffDimm); } @@ -689,8 +689,8 @@ out:
static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) { - uint32_t base0, base1; - uint32_t dch; + u32 base0, base1; + u32 dch;
if (sz.side1 != sz.side2) { sz.side2 = 0; @@ -756,7 +756,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, 0, 0, 5, 8,10, };
- uint32_t map; + u32 map;
map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); @@ -881,7 +881,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) { /* 35 - 25 */ - static const uint8_t csbase_low_shift[] = { + static const u8 csbase_low_shift[] = { /* 32MB */ (13 - 4), /* 64MB */ (14 - 4), /* 128MB */ (14 - 4), @@ -891,7 +891,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) /* 2GB */ (16 - 4), };
- static const uint8_t csbase_low_d0_shift[] = { + static const u8 csbase_low_d0_shift[] = { /* 32MB */ (13 - 4), /* 64MB */ (14 - 4), /* 128MB */ (14 - 4), @@ -907,12 +907,12 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
/* cs_base_high is not changed */
- uint32_t csbase_inc; + u32 csbase_inc; int chip_selects, index; int bits; unsigned common_size; unsigned common_cs_mode; - uint32_t csbase, csmask; + u32 csbase, csmask;
/* See if all of the memory chip selects are the same size * and if so count them. @@ -923,7 +923,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) for (index = 0; index < 8; index++) { unsigned size; unsigned cs_mode; - uint32_t value; + u32 value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
@@ -992,7 +992,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) csmask = (((common_size << bits) - 1) << 21); csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc); for (index = 0; index < 8; index++) { - uint32_t value; + u32 value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); /* Is it enabled? */ @@ -1019,12 +1019,12 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) for (;;) { /* Find the largest remaining candidate */ unsigned index, candidate; - uint32_t csbase, csmask; + u32 csbase, csmask; unsigned size; csbase = 0; candidate = 0; for (index = 0; index < 8; index++) { - uint32_t value; + u32 value; value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */ @@ -1084,7 +1084,7 @@ static unsigned long memory_end_k(const struct mem_controller *ctrl, int max_nod /* Find the last memory address used */ end_k = 0; for (node_id = 0; node_id < max_node_id; node_id++) { - uint32_t limit, base; + u32 limit, base; unsigned index; index = node_id << 3; base = pci_read_config32(ctrl->f1, 0x40 + index); @@ -1135,7 +1135,7 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, int registered; int unbuffered; int has_dualch = is_opteron(ctrl); - uint32_t dcl; + u32 dcl; unbuffered = 0; registered = 0; for (i = 0; (i < DIMM_SOCKETS); i++) { @@ -1216,9 +1216,9 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_mask) { int i; - uint32_t nbcap; + u32 nbcap; /* SPD addresses to verify are identical */ - static const uint8_t addresses[] = { + static const u8 addresses[] = { 2, /* Type should be DDR SDRAM */ 3, /* *Row addresses */ 4, /* *Column addresses */ @@ -1277,7 +1277,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma } } printk(BIOS_SPEW, "Enabling dual channel memory\n"); - uint32_t dcl; + u32 dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_32ByteEn; dcl |= DCL_128BitEn; @@ -1289,16 +1289,16 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma }
struct mem_param { - uint8_t cycle_time; - uint8_t divisor; /* In 1/2 ns increments */ - uint8_t tRC; - uint8_t tRFC; - uint32_t dch_memclk; - uint16_t dch_tref4k, dch_tref8k; - uint8_t dtl_twr; - uint8_t dtl_twtr; - uint8_t dtl_trwt[3][3]; /* first index is CAS_LAT 2/2.5/3 and 128/registered64/64 */ - uint8_t rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */ + u8 cycle_time; + u8 divisor; /* In 1/2 ns increments */ + u8 tRC; + u8 tRFC; + u32 dch_memclk; + u16 dch_tref4k, dch_tref8k; + u8 dtl_twr; + u8 dtl_twtr; + u8 dtl_trwt[3][3]; /* first index is CAS_LAT 2/2.5/3 and 128/registered64/64 */ + u8 rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */ char name[9]; };
@@ -1445,7 +1445,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_ unsigned int dloading = 0, i, rpos = 0, dpos = 0; const unsigned char (*dimm_loading_config)[16] = dimm_loading_config_revE; int rank; - uint32_t dcl; + u32 dcl;
if (is_cpu_pre_e0()) { dimm_loading_config = dimm_loading_config_preE; @@ -1578,9 +1578,9 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * struct spd_set_memclk_result result; unsigned char cl_at_freq[NBCAP_MEMCLK_MASK + 1]; int dimm, freq, max_freq_bios, max_freq_dloading, max_freq_1t; - uint32_t value; + u32 value;
- static const uint8_t spd_min_cycle_time_indices[] = { 9, 23, 25 }; + static const u8 spd_min_cycle_time_indices[] = { 9, 23, 25 }; static const unsigned char cycle_time_at_freq[] = { [NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */ [NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */ @@ -1705,7 +1705,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i) { unsigned clocks, old_clocks; - uint32_t dtl; + u32 dtl; int value; value = spd_read_byte(ctrl->channel0[i], 41); if (value < 0) return -1; @@ -1734,7 +1734,7 @@ static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_p static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i) { unsigned clocks, old_clocks; - uint32_t dtl; + u32 dtl; int value; value = spd_read_byte(ctrl->channel0[i], 42); if (value < 0) return -1; @@ -1763,7 +1763,7 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_ static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i) { unsigned clocks, old_clocks; - uint32_t dtl; + u32 dtl; int value; value = spd_read_byte(ctrl->channel0[i], 29); if (value < 0) return -1; @@ -1788,7 +1788,7 @@ static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_ static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i) { unsigned clocks, old_clocks; - uint32_t dtl; + u32 dtl; int value; value = spd_read_byte(ctrl->channel0[i], 28); if (value < 0) return -1; @@ -1813,7 +1813,7 @@ static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i) { unsigned clocks, old_clocks; - uint32_t dtl; + u32 dtl; int value; value = spd_read_byte(ctrl->channel0[i], 30); if (value < 0) return -1; @@ -1838,7 +1838,7 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_ static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i) { unsigned clocks, old_clocks; - uint32_t dtl; + u32 dtl; int value; value = spd_read_byte(ctrl->channel0[i], 27); if (value < 0) return -1; @@ -1862,7 +1862,7 @@ static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_p
static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dtl; + u32 dtl; dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT); dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT; @@ -1872,7 +1872,7 @@ static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *p
static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dth; + u32 dth; dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT); dth |= (param->dch_tref4k << DTH_TREF_SHIFT); @@ -1881,7 +1881,7 @@ static void init_Tref(const struct mem_controller *ctrl, const struct mem_param
static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i) { - uint32_t dth; + u32 dth; int value; unsigned tref, old_tref; value = spd_read_byte(ctrl->channel0[i], 3); @@ -1909,7 +1909,7 @@ static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_
static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, int i) { - uint32_t dcl; + u32 dcl; int value; #if CONFIG_QRANK_DIMM_SUPPORT int rank; @@ -1944,7 +1944,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
static int update_dimm_ecc(const struct mem_controller *ctrl, const struct mem_param *param, int i) { - uint32_t dcl; + u32 dcl; int value; value = spd_read_byte(ctrl->channel0[i], 11); if (value < 0) { @@ -1964,7 +1964,7 @@ static int count_dimms(const struct mem_controller *ctrl) unsigned index; dimms = 0; for (index = 0; index < 8; index += 2) { - uint32_t csbase; + u32 csbase; csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2))); if (csbase & 1) { dimms += 1; @@ -1975,7 +1975,7 @@ static int count_dimms(const struct mem_controller *ctrl)
static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dth; + u32 dth;
dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT); @@ -1985,7 +1985,7 @@ static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param *
static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dth, dtl; + u32 dth, dtl; unsigned latency; unsigned clocks; int lat, mtype; @@ -2031,7 +2031,7 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param) { /* Memory Clocks after CAS# */ - uint32_t dth; + u32 dth; unsigned clocks; if (is_registered(ctrl)) { clocks = 2; @@ -2047,7 +2047,7 @@ static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *
static void set_read_preamble(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dch; + u32 dch; unsigned rdpreamble; int slots, i;
@@ -2086,7 +2086,7 @@ static void set_read_preamble(const struct mem_controller *ctrl, const struct me
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dch; + u32 dch; unsigned async_lat; int dimms;
@@ -2124,7 +2124,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dch; + u32 dch; /* AMD says to Hardcode this */ dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT); @@ -2229,14 +2229,14 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) }
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) +static u32 hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; - uint32_t carry_over; + u32 carry_over; device_t dev; - uint32_t base, limit; - uint32_t basek; - uint32_t hoist; + u32 base, limit; + u32 basek; + u32 hoist; int j;
carry_over = (4*1024*1024) - hole_startk; @@ -2284,7 +2284,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) {
- uint32_t hole_startk; + u32 hole_startk; int i;
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; @@ -2295,9 +2295,9 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) * If it is equal to the dram base address in K (base_k), * we need to decrease it. */ - uint32_t basek_pri; + u32 basek_pri; for (i=0; i<controllers; i++) { - uint32_t base; + u32 base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -2318,7 +2318,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) #endif /* Find node number that needs the memory hole configured */ for (i=0; i<controllers; i++) { - uint32_t base, limit; + u32 base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -2362,7 +2362,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Before enabling memory start the memory clocks */ for (i = 0; i < controllers; i++) { - uint32_t dch; + u32 dch; if (!controller_present(ctrl + i)) continue; dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); @@ -2372,7 +2372,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } else { /* Disable dram receivers */ - uint32_t dcl; + u32 dcl; dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); dcl |= DCL_DisInRcvrs; pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); @@ -2384,7 +2384,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) memreset(controllers, ctrl);
for (i = 0; i < controllers; i++) { - uint32_t dcl, dch; + u32 dcl, dch; if (!controller_present(ctrl + i)) continue; /* Skip everything if I don't have any memory on this controller */ @@ -2396,7 +2396,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Toggle DisDqsHys to get it working */ dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); if (dcl & DCL_DimmEccEn) { - uint32_t mnc; + u32 mnc; printk(BIOS_SPEW, "ECC enabled\n"); mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; @@ -2434,7 +2434,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) }
for (i = 0; i < controllers; i++) { - uint32_t dcl, dch; + u32 dcl, dch; if (!controller_present(ctrl + i)) continue; /* Skip everything if I don't have any memory on this controller */ @@ -2496,7 +2496,7 @@ static void set_sysinfo_in_ram(unsigned val) }
void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, - const uint16_t *spd_addr) + const u16 *spd_addr) { int i; int j; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index b8417a6..a73cc62 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -725,7 +725,7 @@ static int is_opteron(const struct mem_controller *ctrl) * need to fix up all code using this function, too. */
- uint32_t nbcap; + u32 nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit); } @@ -829,7 +829,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size *sz, unsigned index, struct mem_info *meminfo) { - uint32_t base0, base1; + u32 base0, base1;
/* For each base register. * Place the dimm size in 32 MB quantities in the bits 31 - 21. @@ -876,8 +876,8 @@ static void set_dimm_size(const struct mem_controller *ctrl,
/* Enable the memory clocks for this DIMM by Clear the MemClkDis bit*/ if (base0) { - uint32_t dword; - uint32_t ClkDis0; + u32 dword; + u32 ClkDis0; #if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */ ClkDis0 = DTL_MemClkDis0; #elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */ @@ -936,7 +936,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, struct dimm_size *sz, unsigned index, struct mem_info *meminfo) { - static const uint8_t cs_map_aaa[24] = { + static const u8 cs_map_aaa[24] = { /* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */ //Bank2 0, 1, 3, @@ -950,7 +950,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, 0,10,11, };
- uint32_t map; + u32 map;
if (!(meminfo->dimm_mask & 0x0F) && (meminfo->dimm_mask & 0xF0)) { /* channelB only? */ index += 2; @@ -1080,7 +1080,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, { /* 35 - 27 */
- static const uint8_t csbase_low_f0_shift[] = { + static const u8 csbase_low_f0_shift[] = { /* 128MB */ (14 - (13-5)), /* 256MB */ (15 - (13-5)), /* 512MB */ (15 - (13-5)), @@ -1097,12 +1097,12 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
/* cs_base_high is not changed */
- uint32_t csbase_inc; + u32 csbase_inc; int chip_selects, index; int bits; unsigned common_size; unsigned common_cs_mode; - uint32_t csbase, csmask; + u32 csbase, csmask;
/* See if all of the memory chip selects are the same size * and if so count them. @@ -1122,7 +1122,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, for (index = 0; index < 8; index++) { unsigned size; unsigned cs_mode; - uint32_t value; + u32 value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
@@ -1174,7 +1174,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, csmask = (((common_size << bits) - 1) << 19); csmask |= 0x3fe0 & ~((csbase_inc << bits) - csbase_inc); for (index = 0; index < 8; index++) { - uint32_t value; + u32 value;
value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); /* Is it enabled? */ @@ -1203,12 +1203,12 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) for (;;) { /* Find the largest remaining canidate */ unsigned index, canidate; - uint32_t csbase, csmask; + u32 csbase, csmask; unsigned size; csbase = 0; canidate = 0; for (index = 0; index < 8; index++) { - uint32_t value; + u32 value; value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */ @@ -1270,7 +1270,7 @@ static unsigned long memory_end_k(const struct mem_controller *ctrl, int max_nod /* Find the last memory address used */ end_k = 0; for (node_id = 0; node_id < max_node_id; node_id++) { - uint32_t limit, base; + u32 limit, base; unsigned index; index = node_id << 3; base = pci_read_config32(ctrl->f1, 0x40 + index); @@ -1328,8 +1328,8 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, struct mem_info *meminfo) { int i; - uint32_t registered; - uint32_t dcl; + u32 registered; + u32 dcl; registered = 0; for (i = 0; (i < DIMM_SOCKETS); i++) { int value; @@ -1416,9 +1416,9 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl) static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_info *meminfo) { int i; - uint32_t nbcap; + u32 nbcap; /* SPD addresses to verify are identical */ - static const uint8_t addresses[] = { + static const u8 addresses[] = { 2, /* Type should be DDR2 SDRAM */ 3, /* *Row addresses */ 4, /* *Column addresses */ @@ -1543,14 +1543,14 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i }
struct mem_param { - uint16_t cycle_time; - uint8_t divisor; /* In 1/40 ns increments */ - uint8_t TrwtTO; - uint8_t Twrrd; - uint8_t Twrwr; - uint8_t Trdrd; - uint8_t DcqByPassMax; - uint32_t dch_memclk; + u16 cycle_time; + u8 divisor; /* In 1/40 ns increments */ + u8 TrwtTO; + u8 Twrrd; + u8 Twrwr; + u8 Trdrd; + u8 DcqByPassMax; + u32 dch_memclk; char name[9]; };
@@ -1622,10 +1622,10 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) return param; }
-static uint8_t get_exact_divisor(int i, uint8_t divisor) +static u8 get_exact_divisor(int i, u8 divisor) { //input divisor could be 200(200), 150(266), 120(333), 100 (400) - static const uint8_t dv_a[] = { + static const u8 dv_a[] = { /* 200 266 333 400 */ /*4 */ 250, 250, 250, 250, /*5 */ 200, 200, 200, 100, @@ -1696,7 +1696,7 @@ static unsigned convert_to_linear(unsigned value) return value; }
-static const uint8_t latency_indicies[] = { 25, 23, 9 }; +static const u8 latency_indicies[] = { 25, 23, 9 };
static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time) { @@ -1792,9 +1792,9 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * struct spd_set_memclk_result result; unsigned min_cycle_time, min_latency, bios_cycle_time; int i; - uint32_t value; + u32 value;
- static const uint16_t min_cycle_times[] = { // use full speed to compare + static const u16 min_cycle_times[] = { // use full speed to compare [NBCAP_MEMCLK_NOLIMIT] = 0x250, /*2.5ns */ [NBCAP_MEMCLK_333MHZ] = 0x300, /* 3.0ns */ [NBCAP_MEMCLK_266MHZ] = 0x375, /* 3.75ns */ @@ -1948,7 +1948,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
static unsigned convert_to_1_4(unsigned value) { - static const uint8_t fraction[] = { 0, 1, 2, 2, 3, 3, 0 }; + static const u8 fraction[] = { 0, 1, 2, 2, 3, 3, 0 }; unsigned valuex;
/* We need to convert value to more readable */ @@ -1990,7 +1990,7 @@ static int update_dimm_Trc(const struct mem_controller *ctrl, int i, long dimm_mask) { int clocks, old_clocks; - uint32_t dtl; + u32 dtl; u32 spd_device = ctrl->channel0[i];
if (!(dimm_mask & (1 << i)) && (dimm_mask & (1 << (DIMM_SOCKETS + i)))) { /* channelB only? */ @@ -2020,7 +2020,7 @@ static int update_dimm_Trc(const struct mem_controller *ctrl, static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo) { unsigned clocks, old_clocks; - uint32_t dth; + u32 dth; int value; u8 ch_b = 0; u32 spd_device = ctrl->channel0[i]; @@ -2058,7 +2058,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX ) { unsigned clocks, old_clocks; - uint32_t dtl; + u32 dtl; int value; u32 spd_device = ctrl->channel0[i];
@@ -2106,7 +2106,7 @@ static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask) { unsigned clocks, old_clocks; - uint32_t dtl; + u32 dtl; int value; u32 spd_device = ctrl->channel0[i];
@@ -2156,7 +2156,7 @@ static int update_dimm_Trtp(const struct mem_controller *ctrl, /* need to figure if it is 32 byte burst or 64 bytes burst */ int offset = 2; if (!meminfo->is_Width128) { - uint32_t dword; + u32 dword; dword = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); if ((dword & DCL_BurstLength32)) offset = 0; } @@ -2173,7 +2173,7 @@ static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_p static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask) { - uint32_t dth, dth_old; + u32 dth, dth_old; int value; u32 spd_device = ctrl->channel0[i];
@@ -2226,7 +2226,7 @@ static void set_4RankRDimm(const struct mem_controller *ctrl, }
if (value == 1) { - uint32_t dch; + u32 dch; dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch |= DCH_FourRankRDimm; pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); @@ -2234,15 +2234,15 @@ static void set_4RankRDimm(const struct mem_controller *ctrl, #endif }
-static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, +static u32 get_extra_dimm_mask(const struct mem_controller *ctrl, struct mem_info *meminfo) { int i;
- uint32_t mask_x4; - uint32_t mask_x16; - uint32_t mask_single_rank; - uint32_t mask_page_1k; + u32 mask_x4; + u32 mask_x16; + u32 mask_single_rank; + u32 mask_page_1k; int value; #if CONFIG_QRANK_DIMM_SUPPORT int rank; @@ -2312,7 +2312,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { - uint32_t dcl; + u32 dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~(DCL_X4Dimm_MASK<<DCL_X4Dimm_SHIFT); dcl |= ((meminfo->x4_mask) & 0xf) << (DCL_X4Dimm_SHIFT); @@ -2320,7 +2320,7 @@ static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_para }
-static int count_ones(uint32_t dimm_mask) +static int count_ones(u32 dimm_mask) { int dimms; unsigned index; @@ -2337,7 +2337,7 @@ static int count_ones(uint32_t dimm_mask) static void set_DramTerm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { - uint32_t dcl; + u32 dcl; unsigned odt; odt = 1; // 75 ohms
@@ -2367,7 +2367,7 @@ static void set_ecc(const struct mem_controller *ctrl, int i; int value;
- uint32_t dcl, nbcap; + u32 dcl, nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_DimmEccEn; @@ -2427,7 +2427,7 @@ static void set_TT(const struct mem_controller *ctrl, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX, unsigned val, const char *str) { - uint32_t reg; + u32 reg;
if ((val < TT_MIN) || (val > TT_MAX)) { printk(BIOS_ERR, "%s", str); @@ -2472,8 +2472,8 @@ static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem
static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { - static const uint8_t faw_1k[] = {8, 10, 13, 14}; - static const uint8_t faw_2k[] = {10, 14, 17, 18}; + static const u8 faw_1k[] = {8, 10, 13, 14}; + static const u8 faw_2k[] = {10, 14, 17, 18}; unsigned memclkfreq_index; unsigned faw;
@@ -2491,7 +2491,7 @@ static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dch; + u32 dch; unsigned async_lat;
@@ -2509,7 +2509,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ static void set_SlowAccessMode(const struct mem_controller *ctrl) { - uint32_t dch; + u32 dch;
dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
@@ -2525,8 +2525,8 @@ static void set_SlowAccessMode(const struct mem_controller *ctrl) */ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *meminfo) { - uint32_t dword; - uint32_t dwordx; + u32 dword; + u32 dwordx; #if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ unsigned SlowAccessMode = 0; #endif @@ -2712,7 +2712,7 @@ static void set_RDqsEn(const struct mem_controller *ctrl, { #if CONFIG_CPU_SOCKET_TYPE==0x10 //only need to set for reg and x8 - uint32_t dch; + u32 dch;
dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
@@ -2728,7 +2728,7 @@ static void set_RDqsEn(const struct mem_controller *ctrl, static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { - uint32_t dcm; + u32 dcm; /* AMD says to Hardcode this */ dcm = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC); dcm &= ~(DCM_ILD_lmt_MASK << DCM_ILD_lmt_SHIFT); @@ -2902,14 +2902,14 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, #include "raminit_f_dqs.c"
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) +static u32 hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; - uint32_t carry_over; + u32 carry_over; device_t dev; - uint32_t base, limit; - uint32_t basek; - uint32_t hoist; + u32 base, limit; + u32 basek; + u32 hoist; int j;
carry_over = (4*1024*1024) - hole_startk; @@ -2959,7 +2959,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) {
- uint32_t hole_startk; + u32 hole_startk; int i;
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; @@ -2968,9 +2968,9 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ - uint32_t basek_pri; + u32 basek_pri; for (i=0; i<controllers; i++) { - uint32_t base; + u32 base; unsigned base_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { @@ -2989,7 +2989,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) #endif /* find node index that need do set hole */ for (i=0; i < controllers; i++) { - uint32_t base, limit; + u32 base, limit; unsigned base_k, limit_k; base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1 << 1) | (1 << 0))) != ((1 << 1) | (1 << 0))) { @@ -3029,7 +3029,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, tsc_t tsc, tsc0[8];
printk(BIOS_DEBUG, "sdram_enable: tsc0[8]: %p", &tsc0[0]); - uint32_t dword; + u32 dword; #endif
/* Error if I don't have memory */ @@ -3039,7 +3039,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
/* Before enabling memory start the memory clocks */ for (i = 0; i < controllers; i++) { - uint32_t dch; + u32 dch; if (!sysinfo->ctrl_present[ i ]) continue; dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); @@ -3069,7 +3069,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, }
for (i = 0; i < controllers; i++) { - uint32_t dcl, dch; + u32 dcl, dch; if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ @@ -3081,7 +3081,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, /* ChipKill */ dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); if (dcl & DCL_DimmEccEn) { - uint32_t mnc; + u32 mnc; printk(BIOS_SPEW, "ECC enabled\n"); mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; @@ -3111,7 +3111,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, }
for (i = 0; i < controllers; i++) { - uint32_t dcl, dcm; + u32 dcl, dcm; if (!sysinfo->ctrl_present[ i ]) continue; /* Skip everything if I don't have any memory on this controller */ @@ -3228,7 +3228,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, }
void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, - const uint16_t *spd_addr) + const u16 *spd_addr) { int i; int j; diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 8ab1b47..8d498a4 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -72,12 +72,12 @@ static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ct } static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo) { - uint32_t dword; - uint32_t mem_base; + u32 dword; + u32 mem_base; unsigned nodeid = ctrl->node_id;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - uint32_t hole_reg; + u32 hole_reg; #endif
//get the local base addr of the chipselect @@ -152,7 +152,7 @@ static void clear_wrap32dis(void) {
}
-static void set_FSBASE(uint32_t addr_hi) +static void set_FSBASE(u32 addr_hi) { msr_t msr;
@@ -181,7 +181,8 @@ static unsigned RcvrRankEnabled(const struct mem_controller *ctrl, int channel, return ChipSelPresent(ctrl, cs_idx, sysinfo); }
-static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_num) +static void WriteLNTestPattern(unsigned addr_lo, u8 *buf_a, + unsigned line_num) { __asm__ volatile ( "1:\n\t" @@ -197,9 +198,10 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_n
}
-static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b) +static void Write1LTestPattern(unsigned addr, unsigned p, u8 *buf_a, + u8 *buf_b) { - uint8_t *buf; + u8 *buf; if(p==1) { buf = buf_b; } else { buf = buf_a; }
@@ -237,24 +239,28 @@ static void Read1LTestPattern(unsigned addr) #define SB_SMALLDQS 15
-static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned pattern, const uint32_t *TestPattern0, const uint32_t *TestPattern1, const uint32_t *TestPattern2, unsigned Pass, unsigned is_Width128) +static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned pattern, + const u32 *TestPattern0, + const u32 *TestPattern1, + const u32 *TestPattern2, unsigned Pass, + unsigned is_Width128) { - uint32_t addr_lo; - uint32_t *test_buf; - uint32_t value; - uint32_t value_test; + u32 addr_lo; + u32 *test_buf; + u32 value; + u32 value_test; unsigned result = DQS_FAIL;
if(Pass == DQS_FIRST_PASS) { if(pattern==1) { - test_buf = (uint32_t *)TestPattern1; + test_buf = (u32 *)TestPattern1; } else { - test_buf = (uint32_t *)TestPattern0; + test_buf = (u32 *)TestPattern0; } } else { - test_buf = (uint32_t *)TestPattern2; + test_buf = (u32 *)TestPattern2; }
set_FSBASE(addr>>24); @@ -308,7 +314,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned
static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly) { - uint32_t reg; + u32 reg;
dly += (20-1); // round it dly /= 20; // convert from unit 50ps to 1ns @@ -370,7 +376,7 @@ static void proc_IOCLFLUSH(unsigned addr)
static void ResetDCTWrPtr(const struct mem_controller *ctrl) { - uint32_t dword; + u32 dword; unsigned index = 0x10;
dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index); @@ -383,12 +389,12 @@ static void ResetDCTWrPtr(const struct mem_controller *ctrl) }
-static uint16_t get_exact_T1000(unsigned i) +static u16 get_exact_T1000(unsigned i) { // 200 266, 333, 400 - static const uint16_t T1000_a[]= { 5000, 3759, 3003, 2500 }; + static const u16 T1000_a[]= { 5000, 3759, 3003, 2500 };
- static const uint16_t TT_a[] = { + static const u16 TT_a[] = { /*200 266 333 400 */ /*4 */ 6250, 6250, 6250, 6250, /*5 */ 5000, 5000, 5000, 2500, @@ -437,7 +443,7 @@ static uint16_t get_exact_T1000(unsigned i) static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) { int i; - uint32_t dword; + u32 dword;
dword = 0x00000000; for(i=1; i<=3; i++) { @@ -459,30 +465,30 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl) static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo) {
- static const uint32_t TestPattern0[] = { + static const u32 TestPattern0[] = { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, }; - static const uint32_t TestPattern1[] = { + static const u32 TestPattern1[] = { 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, 0x55555555, }; - static const uint32_t TestPattern2[] = { + static const u32 TestPattern2[] = { 0x12345678, 0x87654321, 0x23456789, 0x98765432, 0x59385824, 0x30496724, 0x24490795, 0x99938733, 0x40385642, 0x38465245, 0x29432163, 0x05067894, 0x12349045, 0x98723467, 0x12387634, 0x34587623, };
- uint8_t pattern_buf_x[64 * 4 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ - uint8_t *buf_a, *buf_b; - uint32_t ecc_bit; - uint32_t dword; - uint8_t *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8] ; //8 node, channel 2, receiver 8 + u8 pattern_buf_x[64 * 4 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ + u8 *buf_a, *buf_b; + u32 ecc_bit; + u32 dword; + u8 *dqs_rcvr_dly_a = &sysinfo->dqs_rcvr_dly_a[ctrl->node_id * 2* 8] ; //8 node, channel 2, receiver 8
int i;
@@ -555,18 +561,18 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st T1000 = get_exact_T1000(dword);
// SetupRcvrPattern - buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); + buf_a = (u8 *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0)); buf_b = buf_a + 128; //?? if(Pass==DQS_FIRST_PASS) { for(i=0;i<16;i++) { - *((uint32_t *)(buf_a + i*4)) = TestPattern0[i]; - *((uint32_t *)(buf_b + i*4)) = TestPattern1[i]; + *((u32 *)(buf_a + i*4)) = TestPattern0[i]; + *((u32 *)(buf_b + i*4)) = TestPattern1[i]; } } else { for(i=0;i<16;i++) { - *((uint32_t *)(buf_a + i*4)) = TestPattern2[i]; - *((uint32_t *)(buf_b + i*4)) = TestPattern2[i]; + *((u32 *)(buf_a + i*4)) = TestPattern2[i]; + *((u32 *)(buf_b + i*4)) = TestPattern2[i]; } }
@@ -855,7 +861,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, unsigned bytelane, unsigned direction, unsigned dqs_delay) { //ByteLane could be 0-8, last is for ECC unsigned index; - uint32_t dword; + u32 dword; unsigned shift;
dqs_delay &= 0xff; @@ -877,7 +883,7 @@ static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel, static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channel, unsigned direction, unsigned dqs_delay) { unsigned index; - uint32_t dword; + u32 dword; int i;
dword = 0; @@ -904,12 +910,14 @@ static unsigned MiddleDQS(unsigned min_d, unsigned max_d) return ( min_d + (size_d>>1)); }
-static inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a, uint8_t dqs_delay) +static inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, + u8 *dqs_delay_a, u8 dqs_delay) { dqs_delay_a[channel * 2*9 + direction * 9 + bytelane] = dqs_delay; }
-static void WriteDQSTestPattern(unsigned addr_lo, unsigned pattern , uint8_t *buf_a) +static void WriteDQSTestPattern(unsigned addr_lo, unsigned pattern , + u8 *buf_a) { WriteLNTestPattern(addr_lo, buf_a, (pattern+1) * 9); } @@ -1040,17 +1048,18 @@ static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern ) } }
-static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsigned pattern, uint8_t *buf_a) +static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsigned pattern, + u8 *buf_a) { - uint32_t *test_buf; + u32 *test_buf; unsigned bitmap = 0xff; unsigned bytelane; int i; - uint32_t value; + u32 value; int j; - uint32_t value_test; + u32 value_test;
- test_buf = (uint32_t *)buf_a; + test_buf = (u32 *)buf_a;
if(pattern && channel) { @@ -1095,7 +1104,9 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign
}
-static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, unsigned Direction, unsigned Pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo) +static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel, unsigned Direction, unsigned Pattern, + u8 *buf_a, u8 *dqs_delay_a, + struct sys_info *sysinfo) { unsigned ByteLane; unsigned Errors; @@ -1218,13 +1229,17 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
}
-static unsigned TrainReadDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo) +static unsigned TrainReadDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, + u8 *buf_a, u8 *dqs_delay_a, + struct sys_info *sysinfo) { print_debug_dqs("\t\tTrainReadPos", 0, 2); return TrainDQSPos(ctrl, channel, DQS_READDIR, pattern, buf_a, dqs_delay_a, sysinfo); }
-static unsigned TrainWriteDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, uint8_t *buf_a, uint8_t *dqs_delay_a, struct sys_info *sysinfo) +static unsigned TrainWriteDQS(const struct mem_controller *ctrl, unsigned channel, unsigned pattern, + u8 *buf_a, u8 *dqs_delay_a, + struct sys_info *sysinfo) { print_debug_dqs("\t\tTrainWritePos", 0, 2); return TrainDQSPos(ctrl, channel, DQS_WRITEDIR, pattern, buf_a, dqs_delay_a, sysinfo); @@ -1234,7 +1249,7 @@ static unsigned TrainWriteDQS(const struct mem_controller *ctrl, unsigned channe
static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info *sysinfo) { - static const uint32_t TestPatternJD1a[] = { + static const u32 TestPatternJD1a[] = { 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW0-1, ALL-EVEN 0x00000000,0x00000000,0x00000000,0x00000000, // QW2-3, ALL-EVEN 0x00000000,0x00000000,0xFFFFFFFF,0xFFFFFFFF, // QW4-5, ALL-EVEN @@ -1272,7 +1287,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in 0x80808080,0x80808080,0x7F7F7F7F,0x7F7F7F7F, // QW4-5, DQ7-ODD 0x80808080,0x80808080,0x80808080,0x80808080 // QW6-7, DQ7-ODD }; - static const uint32_t TestPatternJD1b[] = { + static const u32 TestPatternJD1b[] = { 0x00000000,0x00000000,0x00000000,0x00000000, // QW0,CHA-B, ALL-EVEN 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, // QW1,CHA-B, ALL-EVEN 0x00000000,0x00000000,0x00000000,0x00000000, // QW2,CHA-B, ALL-EVEN @@ -1346,18 +1361,18 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in 0x80808080,0x80808080,0x80808080,0x80808080, // QW6,CHA-B, DQ7-ODD 0x80808080,0x80808080,0x80808080,0x80808080 // QW7,CHA-B, DQ7-ODD }; - uint8_t pattern_buf_x[64 * 18 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ - uint8_t *buf_a; + u8 pattern_buf_x[64 * 18 + 16]; // We need to two cache line So have more 16 bytes to keep 16 byte alignment */ + u8 *buf_a;
unsigned pattern; - uint32_t dword; - uint32_t ecc_bit; + u32 dword; + u32 ecc_bit; unsigned Errors; unsigned channel; int i; unsigned DQSWrDelay; unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128; - uint8_t *dqs_delay_a = &sysinfo->dqs_delay_a[ctrl->node_id * 2*2*9]; //channel 2, direction 2 , bytelane *9 + u8 *dqs_delay_a = &sysinfo->dqs_delay_a[ctrl->node_id * 2*2*9]; //channel 2, direction 2 , bytelane *9
//enable SSE2 enable_sse2(); @@ -1372,18 +1387,18 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dword);
//SetupDqsPattern - buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf)); + buf_a = (u8 *)(((u32)(&pattern_buf_x[0]) + 0x10) & (~0xf));
if(is_Width128){ pattern = 1; for(i=0;i<16*18;i++) { - *((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i]; + *((u32 *)(buf_a + i*4)) = TestPatternJD1b[i]; } } else { pattern = 0; for(i=0; i<16*9;i++) { - *((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i]; + *((u32 *)(buf_a + i*4)) = TestPatternJD1a[i]; }
} @@ -1444,12 +1459,14 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in return Errors;
} -static inline uint8_t get_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a) +static inline u8 get_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, + u8 *dqs_delay_a) { return dqs_delay_a[channel * 2*9 + direction * 9 + bytelane]; }
-static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned ByteLane1, unsigned InterFactor, unsigned Direction, uint8_t *dqs_delay_a) +static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned ByteLane1, unsigned InterFactor, unsigned Direction, + u8 *dqs_delay_a) /* InterFactor: 0: 100% ByteLane 0 0x80: 50% between ByteLane 0 and 1 0xff: 99.6% ByteLane 1 and 0.4% like 0 @@ -1494,7 +1511,7 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info
unsigned direction[] = { DQS_READDIR, DQS_WRITEDIR }; int i; - uint8_t *dqs_delay_a = &sysinfo->dqs_delay_a[ctrl->node_id * 2*2*9]; //channel 2, direction 2 , bytelane *9 + u8 *dqs_delay_a = &sysinfo->dqs_delay_a[ctrl->node_id * 2*2*9]; //channel 2, direction 2 , bytelane *9
ByteLane = 8;
@@ -1551,7 +1568,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl /* Skip everything if I don't have any memory on this controller */ if(sysinfo->meminfo[i].dimm_mask==0x00) continue;
- uint32_t dword; + u32 dword;
cpu_f0_f1[i] = is_cpu_pre_f2_in_bsp(i);
@@ -1781,7 +1798,7 @@ static void clear_mtrr_dqs(unsigned tom2_k) #if CONFIG_MEM_TRAIN_SEQ == 1 static void set_htic_bit(unsigned i, unsigned val, unsigned bit) { - uint32_t dword; + u32 dword; dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL); dword &= ~(1<<bit); dword |= ((val & 1) <<bit); @@ -1790,7 +1807,7 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
static unsigned get_htic_bit(unsigned i, unsigned bit) { - uint32_t dword; + u32 dword; dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL); dword &= (1<<bit); return dword; diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index fd2107c..57a1287 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -32,24 +32,24 @@ typedef unsigned device_t;
unsigned char pci_register[256*5*3*256];
-static uint8_t pci_read_config8(device_t dev, unsigned where) +static u8 pci_read_config8(device_t dev, unsigned where) { unsigned addr; addr = dev | where; return pci_register[addr]; }
-static uint16_t pci_read_config16(device_t dev, unsigned where) +static u16 pci_read_config16(device_t dev, unsigned where) { unsigned addr; addr = dev | where; return pci_register[addr] | (pci_register[addr + 1] << 8); }
-static uint32_t pci_read_config32(device_t dev, unsigned where) +static u32 pci_read_config32(device_t dev, unsigned where) { unsigned addr; - uint32_t value; + u32 value; addr = dev | where; value = pci_register[addr] | (pci_register[addr + 1] << 8) | @@ -67,14 +67,14 @@ static uint32_t pci_read_config32(device_t dev, unsigned where)
}
-static void pci_write_config8(device_t dev, unsigned where, uint8_t value) +static void pci_write_config8(device_t dev, unsigned where, u8 value) { unsigned addr; addr = dev | where; pci_register[addr] = value; }
-static void pci_write_config16(device_t dev, unsigned where, uint16_t value) +static void pci_write_config16(device_t dev, unsigned where, u16 value) { unsigned addr; addr = dev | where; @@ -82,7 +82,7 @@ static void pci_write_config16(device_t dev, unsigned where, uint16_t value) pci_register[addr + 1] = (value >> 8) & 0xff; }
-static void pci_write_config32(device_t dev, unsigned where, uint32_t value) +static void pci_write_config32(device_t dev, unsigned where, u32 value) { unsigned addr; addr = dev | where; @@ -188,7 +188,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) }
-static uint8_t spd_mt4lsdt464a[256] = +static u8 spd_mt4lsdt464a[256] = { 0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70, 0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01, @@ -200,7 +200,7 @@ static uint8_t spd_mt4lsdt464a[256] = 0x06, 0x07, 0x08, 0x09, 0x00, };
-static uint8_t spd_micron_512MB_DDR333[256] = +static u8 spd_micron_512MB_DDR333[256] = { 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, @@ -230,7 +230,7 @@ static uint8_t spd_micron_512MB_DDR333[256] = 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-static uint8_t spd_micron_256MB_DDR333[256] = +static u8 spd_micron_256MB_DDR333[256] = { 0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01, @@ -261,7 +261,7 @@ static uint8_t spd_micron_256MB_DDR333[256] = };
#define MAX_DIMMS 16 -static uint8_t spd_data[MAX_DIMMS*256]; +static u8 spd_data[MAX_DIMMS*256];
static unsigned spd_count, spd_fail_count; static int spd_read_byte(unsigned device, unsigned address) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 770b663..7c0aec4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2634,9 +2634,9 @@ static void Set_OtherTiming(struct MCTStatStruc *pMCTstat, static void Get_Trdrd(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { - int8_t Trdrd; + s8 Trdrd;
- Trdrd = ((int8_t)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 1; + Trdrd = ((s8)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 1; if (Trdrd > 8) Trdrd = 8; pDCTstat->Trdrd = Trdrd; @@ -2645,9 +2645,9 @@ static void Get_Trdrd(struct MCTStatStruc *pMCTstat, static void Get_Twrwr(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { - int8_t Twrwr = 0; + s8 Twrwr = 0;
- Twrwr = ((int8_t)(pDCTstat->WrDatGrossMax - pDCTstat->WrDatGrossMin) >> 1) + 2; + Twrwr = ((s8)(pDCTstat->WrDatGrossMax - pDCTstat->WrDatGrossMin) >> 1) + 2;
if (Twrwr < 2) Twrwr = 2; @@ -2661,11 +2661,11 @@ static void Get_Twrrd(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { u8 LDplus1; - int8_t Twrrd; + s8 Twrrd;
LDplus1 = Get_Latency_Diff(pMCTstat, pDCTstat, dct);
- Twrrd = ((int8_t)(pDCTstat->WrDatGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 4 - LDplus1; + Twrrd = ((s8)(pDCTstat->WrDatGrossMax - pDCTstat->DqsRcvEnGrossMin) >> 1) + 4 - LDplus1;
if (Twrrd < 2) Twrrd = 2; @@ -2678,11 +2678,11 @@ static void Get_TrwtTO(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { u8 LDplus1; - int8_t TrwtTO; + s8 TrwtTO;
LDplus1 = Get_Latency_Diff(pMCTstat, pDCTstat, dct);
- TrwtTO = ((int8_t)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->WrDatGrossMin) >> 1) + LDplus1; + TrwtTO = ((s8)(pDCTstat->DqsRcvEnGrossMax - pDCTstat->WrDatGrossMin) >> 1) + LDplus1;
pDCTstat->TrwtTO = TrwtTO; } diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c index b58519f..1684a39 100644 --- a/src/northbridge/amd/gx2/grphinit.c +++ b/src/northbridge/amd/gx2/grphinit.c @@ -54,7 +54,7 @@ void geodegx2_vga_msr_init(void) /* This function mirrors the Graphics_Init routine in GeodeROM. */ void graphics_init(void) { - uint16_t wClassIndex, wData, res; + u16 wClassIndex, wData, res;
/* SoftVG initialization */ printk(BIOS_DEBUG, "Graphics init...\n"); diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..3865bc1 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -227,7 +227,7 @@ static void northbridge_init(device_t dev)
static void northbridge_set_resources(struct device *dev) { - uint8_t line; + u8 line;
struct bus *bus;
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index 0cb7803..8b5be85 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -421,12 +421,12 @@ static void GeodeLinkPriority(void) * If the setShadow function is used then all shadow descriptors * will stay sync'ed. */ -static uint64_t getShadow(void) +static u64 getShadow(void) { msr_t msr = { 0, 0 };
msr = rdmsr(GLIU0_P2D_SC_0); - return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; + return ( ( (u64) msr.hi ) << 32 ) | msr.lo; }
/* Set the cache RConf registers for the memory hole. @@ -436,13 +436,13 @@ static uint64_t getShadow(void) * * Entry: EDX:EAX is the shadow settings. */ -static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) +static void setShadowRCONF(u32 shadowHi, u32 shadowLo) { /* ok this is whacky bit translation time. */ int bit; - uint8_t shadowByte; + u8 shadowByte; msr_t msr = { 0, 0 }; - shadowByte = (uint8_t) (shadowLo >> 16); + shadowByte = (u8) (shadowLo >> 16);
/* load up D000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { @@ -462,7 +462,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
wrmsr(CPU_RCONF_C0_DF, msr);
- shadowByte = (uint8_t) (shadowLo >> 24); + shadowByte = (u8) (shadowLo >> 24);
/* load up F000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { @@ -487,7 +487,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) * Keeps all cache shadow descriptors sync'ed. * Entry: EDX:EAX is the shadow settings */ -static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) +static void setShadowGLPCI(u32 shadowHi, u32 shadowLo) { msr_t msr;
@@ -502,15 +502,15 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) * Keeps all shadow descriptors sync'ed. * Entry: EDX:EAX is the shadow settings */ -static void setShadow(uint64_t shadowSettings) +static void setShadow(u64 shadowSettings) { int i; msr_t msr; struct gliutable *pTable; - uint32_t shadowLo, shadowHi; + u32 shadowLo, shadowHi;
- shadowLo = (uint32_t) shadowSettings; - shadowHi = (uint32_t) (shadowSettings >> 32); + shadowLo = (u32) shadowSettings; + shadowHi = (u32) (shadowSettings >> 32);
setShadowRCONF(shadowHi, shadowLo); setShadowGLPCI(shadowHi, shadowLo); @@ -520,9 +520,9 @@ static void setShadow(uint64_t shadowSettings) if (pTable->desc_type == SC_SHADOW) {
msr = rdmsr(pTable->desc_name); - msr.lo = (uint32_t) shadowSettings; + msr.lo = (u32) shadowSettings; msr.hi &= 0xFFFF0000; /* maintain PDID in upper EDX */ - msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF; + msr.hi |= ((u32) (shadowSettings >> 32)) & 0x0000FFFF; wrmsr(pTable->desc_name, msr); /* MSR - See the table above */
} @@ -532,9 +532,9 @@ static void setShadow(uint64_t shadowSettings)
static void rom_shadow_settings(void) { - uint64_t shadowSettings = getShadow(); - shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; /* Disable read & writes */ - shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; /* Enable reads for C0000-FFFFF */ + u64 shadowSettings = getShadow(); + shadowSettings &= (u64) 0xFFFF00000000FFFFULL; /* Disable read & writes */ + shadowSettings |= (u64) 0x0000FFFFFFFF0000ULL; /* Enable reads for C0000-FFFFF */ setShadow(shadowSettings); }
@@ -557,7 +557,7 @@ static void enable_L_cache(void) struct gliutable *gl = 0; int i; msr_t msr; - uint8_t SysMemCacheProp; + u8 SysMemCacheProp;
/* Locate SYSMEM entry in GLIU0table */ for (i = 0; gliu0table[i].desc_name != GL_END; i++) { @@ -601,7 +601,7 @@ static void enable_L_cache(void) /* RCONF_BYPASS: Cache tablewalk properties and SMM header access properties. */ /* Set to match system memory cache properties. */ msr = rdmsr(CPU_RCONF_DEFAULT); - SysMemCacheProp = (uint8_t) (msr.lo & 0xFF); + SysMemCacheProp = (u8) (msr.lo & 0xFF); msr = rdmsr(CPU_RCONF_BYPASS); msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp; wrmsr(CPU_RCONF_BYPASS, msr); @@ -625,10 +625,10 @@ static void setup_gx2_cache(void) wbinvd(); }
-uint32_t get_systop(void) +u32 get_systop(void) { struct gliutable *gl = 0; - uint32_t systop; + u32 systop; msr_t msr; int i;
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c index d9af161..f1ead64 100644 --- a/src/northbridge/amd/gx2/raminit.c +++ b/src/northbridge/amd/gx2/raminit.c @@ -39,9 +39,9 @@ static void __attribute__((noreturn)) hcf(void)
static void auto_size_dimm(unsigned int dimm) { - uint32_t dimm_setting; - uint16_t dimm_size; - uint8_t spd_byte; + u32 dimm_setting; + u16 dimm_size; + u8 spd_byte; msr_t msr;
dimm_setting = 0; @@ -166,8 +166,8 @@ static void auto_size_dimm(unsigned int dimm)
static void checkDDRMax(void) { - uint8_t spd_byte0, spd_byte1; - uint16_t speed; + u8 spd_byte0, spd_byte1; + u16 speed;
/* PC133 identifier */ spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); @@ -195,12 +195,12 @@ static void checkDDRMax(void) } }
-const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */ +const u16 REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
static void set_refresh_rate(void) { - uint8_t spd_byte0, spd_byte1; - uint16_t rate0, rate1; + u8 spd_byte0, spd_byte1; + u16 rate0, rate1; msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH); @@ -228,7 +228,7 @@ static void set_refresh_rate(void) wrmsr(MC_CF07_DATA, msr); }
-const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */ +const u8 CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */
static u8 getcasmap(u32 dimm, u16 glspeed) { @@ -259,7 +259,7 @@ static u8 getcasmap(u32 dimm, u16 glspeed) } } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ /* set the casmap based on the shift to limit possible CAS settings */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap); + spd_byte = 31 - __builtin_clz((u32) casmap); /* just want bits in the lower byte since we have to cast to a 32 */ casmap &= 0xFF << (spd_byte - casmap_shift); } else { /* No DIMM */ @@ -289,8 +289,8 @@ static void setCAS(void) * Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. * Destroys: We really use everything ! */ - uint16_t glspeed; - uint8_t spd_byte, casmap0, casmap1; + u16 glspeed; + u8 spd_byte, casmap0, casmap1; msr_t msr;
glspeed = GeodeLinkSpeed(); @@ -319,8 +319,8 @@ static void setCAS(void)
static void set_latencies(void) { - uint32_t memspeed, dimm_setting; - uint8_t spd_byte0, spd_byte1; + u32 memspeed, dimm_setting; + u8 spd_byte0, spd_byte1; msr_t msr;
memspeed = GeodeLinkSpeed() / 2; @@ -422,7 +422,7 @@ static void set_latencies(void)
static void set_extended_mode_registers(void) { - uint8_t spd_byte0, spd_byte1; + u8 spd_byte0, spd_byte1; msr_t msr; spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL); if (spd_byte0 == 0xFF) { @@ -447,7 +447,7 @@ static void set_extended_mode_registers(void) static void sdram_set_registers(const struct mem_controller *ctrl) { msr_t msr; - uint32_t msrnum; + u32 msrnum;
/* Set Refresh Staggering */ msrnum = MC_CF07_DATA; @@ -459,7 +459,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
static void sdram_set_spd_registers(const struct mem_controller *ctrl) { - uint8_t spd_byte; + u8 spd_byte;
printk(BIOS_DEBUG, "sdram_set_spd_register\n"); post_code(POST_MEM_SETUP); /* post_70h */ diff --git a/src/northbridge/amd/lx/grphinit.c b/src/northbridge/amd/lx/grphinit.c index 4537881..f9764ec 100644 --- a/src/northbridge/amd/lx/grphinit.c +++ b/src/northbridge/amd/lx/grphinit.c @@ -67,7 +67,7 @@ void geodelx_vga_msr_init(void) */ void graphics_init(void) { - uint16_t wClassIndex, wData, res; + u16 wClassIndex, wData, res;
/* SoftVG initialization */ printk(BIOS_DEBUG, "Graphics init...\n"); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..8890b99 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -316,7 +316,7 @@ static void northbridge_init(device_t dev)
static void northbridge_set_resources(struct device *dev) { - uint8_t line; + u8 line;
#if 0 struct resource *res; diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index b4e1d4a..d49eb7f 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -465,12 +465,12 @@ static void GeodeLinkPriority(void) * If the setShadow function is used then all shadow descriptors * will stay sync'ed. */ -static uint64_t getShadow(void) +static u64 getShadow(void) { msr_t msr;
msr = rdmsr(MSR_GLIU0_SHADOW); - return (((uint64_t) msr.hi) << 32) | msr.lo; + return (((u64) msr.hi) << 32) | msr.lo; }
/* @@ -479,14 +479,14 @@ static uint64_t getShadow(void) * This is part of the PCI lockup solution * Entry: EDX:EAX is the shadow settings */ -static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) +static void setShadowRCONF(u32 shadowHi, u32 shadowLo) {
// ok this is whacky bit translation time. int bit; - uint8_t shadowByte; + u8 shadowByte; msr_t msr = { 0, 0 }; - shadowByte = (uint8_t) (shadowLo >> 16); + shadowByte = (u8) (shadowLo >> 16);
// load up D000 settings in edx. for (bit = 8; (bit > 4); bit--) { @@ -506,7 +506,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
wrmsr(CPU_RCONF_C0_DF, msr);
- shadowByte = (uint8_t) (shadowLo >> 24); + shadowByte = (u8) (shadowLo >> 24);
// load up F000 settings in edx. for (bit = 8; (bit > 4); bit--) { @@ -532,7 +532,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) * Keeps all cache shadow descriptors sync'ed. * Entry: EDX:EAX is the shadow settings */ -static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) +static void setShadowGLPCI(u32 shadowHi, u32 shadowLo) { msr_t msr;
@@ -548,15 +548,15 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) * Keeps all shadow descriptors sync'ed. * Entry: EDX:EAX is the shadow settings */ -static void setShadow(uint64_t shadowSettings) +static void setShadow(u64 shadowSettings) { int i; msr_t msr; struct gliutable *pTable; - uint32_t shadowLo, shadowHi; + u32 shadowLo, shadowHi;
- shadowLo = (uint32_t) shadowSettings; - shadowHi = (uint32_t) (shadowSettings >> 32); + shadowLo = (u32) shadowSettings; + shadowHi = (u32) (shadowSettings >> 32);
setShadowRCONF(shadowHi, shadowLo); setShadowGLPCI(shadowHi, shadowLo); @@ -567,10 +567,10 @@ static void setShadow(uint64_t shadowSettings) if (pTable->desc_type == SC_SHADOW) {
msr = rdmsr(pTable->desc_name); - msr.lo = (uint32_t) shadowSettings; + msr.lo = (u32) shadowSettings; msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX msr.hi |= - ((uint32_t) (shadowSettings >> 32)) & + ((u32) (shadowSettings >> 32)) & 0x0000FFFF; wrmsr(pTable->desc_name, msr); // MSR - See the table above } @@ -581,10 +581,10 @@ static void setShadow(uint64_t shadowSettings) static void rom_shadow_settings(void) {
- uint64_t shadowSettings = getShadow(); - shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes - shadowSettings |= (uint64_t) 0x00000000F0000000ULL; // Enable reads for F0000-FFFFF - shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable rw for C0000-CFFFF + u64 shadowSettings = getShadow(); + shadowSettings &= (u64) 0xFFFF00000000FFFFULL; // Disable read & writes + shadowSettings |= (u64) 0x00000000F0000000ULL; // Enable reads for F0000-FFFFF + shadowSettings |= (u64) 0x0000FFFFFFFF0000ULL; // Enable rw for C0000-CFFFF setShadow(shadowSettings); }
@@ -611,7 +611,7 @@ static void enable_L1_cache(void) struct gliutable *gl = 0; int i; msr_t msr; - uint8_t SysMemCacheProp; + u8 SysMemCacheProp;
/* Locate SYSMEM entry in GLIU0table */ for (i = 0; gliu0table[i].desc_name != GL_END; i++) { @@ -656,7 +656,7 @@ static void enable_L1_cache(void) // RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. // Set to match system memory cache properties. msr = rdmsr(CPU_RCONF_DEFAULT); - SysMemCacheProp = (uint8_t) (msr.lo & 0xFF); + SysMemCacheProp = (u8) (msr.lo & 0xFF); msr = rdmsr(CPU_RCONF_BYPASS); msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp; @@ -716,7 +716,7 @@ static void setup_lx_cache(void)
unsigned long get_top_of_ram(void) { - uint32_t systop; + u32 systop; msr_t msr;
msr = rdmsr(MSR_GLIU0_SYSMEM); diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 7c95ab4..f9a7f14 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -49,9 +49,9 @@ static void __attribute__((noreturn)) hcf(void)
static void auto_size_dimm(unsigned int dimm) { - uint32_t dimm_setting; - uint16_t dimm_size; - uint8_t spd_byte; + u32 dimm_setting; + u16 dimm_size; + u8 spd_byte; msr_t msr;
dimm_setting = 0; @@ -171,8 +171,8 @@ static void auto_size_dimm(unsigned int dimm)
static void checkDDRMax(void) { - uint8_t spd_byte0, spd_byte1; - uint16_t speed; + u8 spd_byte0, spd_byte1; + u16 speed;
/* PC133 identifier */ spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); @@ -207,12 +207,12 @@ static void checkDDRMax(void) } }
-const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */ +const u16 REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
static void set_refresh_rate(void) { - uint8_t spd_byte0, spd_byte1; - uint16_t rate0, rate1; + u8 spd_byte0, spd_byte1; + u16 rate0, rate1; msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH); @@ -240,7 +240,7 @@ static void set_refresh_rate(void) wrmsr(MC_CF07_DATA, msr); }
-const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */ +const u8 CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */
static u8 getcasmap(u32 dimm, u16 glspeed) { @@ -271,7 +271,7 @@ static u8 getcasmap(u32 dimm, u16 glspeed) } } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ /* set the casmap based on the shift to limit possible CAS settings */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap); + spd_byte = 31 - __builtin_clz((u32) casmap); /* just want bits in the lower byte since we have to cast to a 32 */ casmap &= 0xFF << (spd_byte - casmap_shift); } else { /* No DIMM */ @@ -302,8 +302,8 @@ static void setCAS(void) ;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. ;* Destroys: We really use everything ! ;*****************************************************************************/ - uint16_t glspeed; - uint8_t spd_byte, casmap0, casmap1; + u16 glspeed; + u8 spd_byte, casmap0, casmap1; msr_t msr;
glspeed = GeodeLinkSpeed(); @@ -332,8 +332,8 @@ static void setCAS(void)
static void set_latencies(void) { - uint32_t memspeed, dimm_setting; - uint8_t spd_byte0, spd_byte1; + u32 memspeed, dimm_setting; + u8 spd_byte0, spd_byte1; msr_t msr;
memspeed = GeodeLinkSpeed() / 2; @@ -471,7 +471,7 @@ static void set_latencies(void)
static void set_extended_mode_registers(void) { - uint8_t spd_byte0, spd_byte1; + u8 spd_byte0, spd_byte1; msr_t msr; spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL); if (spd_byte0 == 0xFF) { @@ -520,7 +520,7 @@ static void EnableMTest(void) void sdram_set_registers(const struct mem_controller *ctrl) { msr_t msr; - uint32_t msrnum; + u32 msrnum;
/* Set Timing Control */ msrnum = MC_CF1017_DATA; @@ -549,7 +549,7 @@ void sdram_set_registers(const struct mem_controller *ctrl)
void sdram_set_spd_registers(const struct mem_controller *ctrl) { - uint8_t spd_byte; + u8 spd_byte;
banner("sdram_set_spd_register"); post_code(POST_MEM_SETUP); // post_70h @@ -607,7 +607,7 @@ void sdram_set_spd_registers(const struct mem_controller *ctrl) * Section 4.1.4, GX/CS5535 GeodeROM Porting guide */ void sdram_enable(int controllers, const struct mem_controller *ctrl) { - uint32_t i, msrnum; + u32 i, msrnum; msr_t msr;
/********************************************************************* diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ca8fa27..212a8c9 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -622,9 +622,9 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint64_t topmem = bsp_topmem(); - uint64_t topmem2 = bsp_topmem2(); - uint32_t sysmem_mb, sysmem_gb; + u64 topmem = bsp_topmem(); + u64 topmem2 = bsp_topmem2(); + u32 sysmem_mb, sysmem_gb;
/* refer to UMA_AUTO size computation in Family16h BKDG. */ /* Please reference MemNGetUmaSizeML() */ @@ -799,7 +799,7 @@ static void domain_set_resources(device_t dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + u64 topmem2 = bsp_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } diff --git a/src/northbridge/dmp/vortex86ex/northbridge.c b/src/northbridge/dmp/vortex86ex/northbridge.c index fcebed8..df689a8 100644 --- a/src/northbridge/dmp/vortex86ex/northbridge.c +++ b/src/northbridge/dmp/vortex86ex/northbridge.c @@ -78,7 +78,7 @@ static void set_cmos_memory_size(unsigned long sizek) static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + u32 pci_tolm;
printk(BIOS_SPEW, "Entering vortex86ex pci_domain_set_resources.\n");
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c index 07f1596..2e82b7a 100644 --- a/src/northbridge/intel/e7501/debug.c +++ b/src/northbridge/intel/e7501/debug.c @@ -19,7 +19,7 @@ static inline void print_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -64,7 +64,7 @@ static inline void dump_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -81,7 +81,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn) for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -226,7 +226,7 @@ static inline void dump_io_resources(unsigned port) print_debug(":\n"); #endif for(i=0;i<256;i++) { - uint8_t val; + u8 val; if ((i & 0x0f) == 0) { #if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x:", i); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 64bf840..8e409f8 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -23,7 +23,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + u32 pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; @@ -35,7 +35,7 @@ static void pci_domain_set_resources(device_t dev) * too confusing to get right. Kilobytes are good up to * 4 Terabytes of RAM... */ - uint16_t tolm_r, remapbase_r, remaplimit_r; + u16 tolm_r, remapbase_r, remaplimit_r; unsigned long tomk, tolmk; unsigned long remapbasek, remaplimitk; int idx; diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c index 2247a25..6fc5056 100644 --- a/src/northbridge/intel/e7501/raminit.c +++ b/src/northbridge/intel/e7501/raminit.c @@ -51,7 +51,7 @@ struct dimm_size { unsigned long side2; };
-static const uint32_t refresh_frequency[] = { +static const u32 refresh_frequency[] = { /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) * 0 == least frequent refresh (longest interval between refreshes) @@ -67,7 +67,7 @@ static const uint32_t refresh_frequency[] = { 0, 2, 3, 1, 0, 0, 0, 4 };
-static const uint32_t refresh_rate_map[] = { +static const u32 refresh_rate_map[] = { /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode * Select values (array value) * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 @@ -83,10 +83,10 @@ static const uint32_t refresh_rate_map[] = { 1, 7, 2, 1, 1, 3 };
-#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) +#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(u32)) - 1)
// SPD parameters that must match for dual-channel operation -static const uint8_t dual_channel_parameters[] = { +static const u8 dual_channel_parameters[] = { SPD_MEMORY_TYPE, SPD_MODULE_VOLTAGE, SPD_NUM_COLUMNS, @@ -434,19 +434,19 @@ static const long constant_register_values[] = { /* DDR RECOMP tables */
// Slew table for 1x drive? -static const uint32_t maybe_1x_slew_table[] = { +static const u32 maybe_1x_slew_table[] = { 0x44332211, 0xc9776655, 0xffffffff, 0xffffffff, 0x22111111, 0x55444332, 0xfffca876, 0xffffffff, };
// Slew table for 2x drive? -static const uint32_t maybe_2x_slew_table[] = { +static const u32 maybe_2x_slew_table[] = { 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff, };
// Pull Up / Pull Down offset table, if analogous to IXP2800? -static const uint32_t maybe_pull_updown_offset_table[] = { +static const u32 maybe_pull_updown_offset_table[] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x88888888, 0x88888888, 0x88888888, 0x88888888, }; @@ -497,9 +497,9 @@ Serial presence detect (SPD) functions: * @param dimm_socket_address SMBus address of DIMM socket to interrogate. * @return log2(page size) for each side of the DIMM. */ -static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) +static struct dimm_size sdram_spd_get_page_size(u16 dimm_socket_address) { - uint16_t module_data_width; + u16 module_data_width; int value; struct dimm_size pgsz;
@@ -560,7 +560,7 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) * @param dimm_socket_address SMBus address of DIMM socket to interrogate. * @return Width in bits of each DIMM side's DRAMs. */ -static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) +static struct dimm_size sdram_spd_get_width(u16 dimm_socket_address) { int value; struct dimm_size width; @@ -661,11 +661,11 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) * @return 1 if both DIMM sockets report the same value for the specified * SPD parameter, 0 if the values differed or an error occurred. */ -static uint8_t are_spd_values_equal(uint8_t spd_byte_number, - uint16_t dimm0_address, - uint16_t dimm1_address) +static u8 are_spd_values_equal(u8 spd_byte_number, + u16 dimm0_address, + u16 dimm1_address) { - uint8_t bEqual = 0; + u8 bEqual = 0; int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
@@ -695,10 +695,10 @@ static uint8_t are_spd_values_equal(uint8_t spd_byte_number, * ... * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 */ -static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) +static u8 spd_get_supported_dimms(const struct mem_controller *ctrl) { int i; - uint8_t dimm_mask = 0; + u8 dimm_mask = 0;
// Have to increase size of dimm_mask if this assertion is violated ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4); @@ -709,9 +709,9 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- uint16_t channel0_dimm = ctrl->channel0[i]; - uint16_t channel1_dimm = ctrl->channel1[i]; - uint8_t bDualChannel = 1; + u16 channel0_dimm = ctrl->channel0[i]; + u16 channel1_dimm = ctrl->channel1[i]; + u8 bDualChannel = 1; #ifdef VALIDATE_DIMM_COMPATIBILITY struct dimm_size page_size; struct dimm_size sdram_width; @@ -841,12 +841,12 @@ SDRAM configuration functions: * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the * register value in JEDEC format. */ -static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) +static void do_ram_command(u8 command, u16 jedec_mode_bits) { int i; - uint32_t dram_controller_mode; - uint8_t dimm_start_64M_multiple = 0; - uint16_t e7501_mode_bits = jedec_mode_bits; + u32 dram_controller_mode; + u8 dimm_start_64M_multiple = 0; + u16 e7501_mode_bits = jedec_mode_bits;
// Configure the RAM command dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); @@ -883,7 +883,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
- uint8_t dimm_end_64M_multiple = + u8 dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
@@ -893,7 +893,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
// NOTE: 2^26 == 64 MB
- uint32_t dimm_start_address = + u32 dimm_start_address = dimm_start_64M_multiple << 26;
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); @@ -919,11 +919,11 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the * register value in JEDEC format. */ -static void set_ram_mode(uint16_t jedec_mode_bits) +static void set_ram_mode(u16 jedec_mode_bits) { ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
- uint32_t dram_cas_latency = + u32 dram_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
switch (dram_cas_latency) { @@ -959,7 +959,9 @@ DIMM-independant configuration functions: * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). * @return New multiple of 64 MB total DRAM in the system. */ -static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) +static u8 configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, + u8 total_dram_64M_multiple, + unsigned dimm_index) { int i;
@@ -1023,10 +1025,10 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ static void configure_e7501_ram_addresses(const struct mem_controller - *ctrl, uint8_t dimm_mask) + *ctrl, u8 dimm_mask) { int i; - uint8_t total_dram_64M_multiple = 0; + u8 total_dram_64M_multiple = 0;
// Configure the E7501's DRAM row boundaries // Start by zeroing out the temporary initial configuration @@ -1035,7 +1037,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- uint16_t dimm_socket_address = ctrl->channel0[i]; + u16 dimm_socket_address = ctrl->channel0[i]; struct dimm_size sz;
if (!(dimm_mask & (1 << i))) @@ -1082,11 +1084,11 @@ static void configure_e7501_ram_addresses(const struct mem_controller // Round up to 128MB granularity // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
- uint8_t total_dram_128M_multiple = + u8 total_dram_128M_multiple = (total_dram_64M_multiple + 1) >> 1;
// Convert to high 16 bits of address - uint16_t top_of_low_memory = + u16 top_of_low_memory = total_dram_128M_multiple << 11;
pci_write_config16(PCI_DEV(0, 0, 0), TOLM, @@ -1097,8 +1099,8 @@ static void configure_e7501_ram_addresses(const struct mem_controller // > 3 GB total RAM
// Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory - uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0 - uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF + u16 remap_base = total_dram_64M_multiple; // A[25:0] == 0 + u16 remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF
// Put TOLM at 3 GB
@@ -1129,7 +1131,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller */ static void initialize_ecc(void) { - uint32_t dram_controller_mode; + u32 dram_controller_mode;
/* Test to see if ECC support is enabled */ dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); @@ -1137,7 +1139,7 @@ static void initialize_ecc(void) dram_controller_mode &= 3; if (dram_controller_mode == 2) {
- uint8_t byte; + u8 byte;
RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); /* Initialize ECC bits , use ECC zero mode (new to 7501) */ @@ -1177,15 +1179,15 @@ static void initialize_ecc(void) * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, - uint8_t dimm_mask) + u8 dimm_mask) { int i; - uint32_t dram_timing; + u32 dram_timing; int value; - uint8_t slowest_row_precharge = 0; - uint8_t slowest_ras_cas_delay = 0; - uint8_t slowest_active_to_precharge_delay = 0; - uint32_t current_cas_latency = + u8 slowest_row_precharge = 0; + u8 slowest_ras_cas_delay = 0; + u8 slowest_active_to_precharge_delay = 0; + u32 current_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
// CAS# latency must be programmed beforehand @@ -1195,7 +1197,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, // Each timing parameter is determined by the slowest DIMM
for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - uint16_t dimm_socket_address; + u16 dimm_socket_address;
if (!(dimm_mask & (1 << i))) continue; // This DIMM not present @@ -1311,24 +1313,24 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, - uint8_t dimm_mask) + u8 dimm_mask) { int i; int value; - uint32_t dram_timing; - uint16_t maybe_dram_read_timing; - uint32_t dword; + u32 dram_timing; + u16 maybe_dram_read_timing; + u32 dword;
// CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format // NOTE: E7501 supports only 2.0 and 2.5 - uint32_t system_compatible_cas_latencies = + u32 system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; - uint32_t current_cas_latency; - uint32_t dimm_compatible_cas_latencies; + u32 current_cas_latency; + u32 dimm_compatible_cas_latencies;
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
- uint16_t dimm_socket_address; + u16 dimm_socket_address;
if (!(dimm_mask & (1 << i))) continue; // This DIMM not usable @@ -1410,7 +1412,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, maybe_dram_read_timing |= 0xBB1; } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
- uint32_t dram_row_attributes = + u32 dram_row_attributes = pci_read_config32(PCI_DEV(0, 0, 0), DRA);
dram_timing |= DRT_CAS_2_5; @@ -1468,14 +1470,14 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, */ static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl, - uint8_t dimm_mask) + u8 dimm_mask) { int i;
// Initial settings - uint32_t controller_mode = + u32 controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); - uint32_t system_refresh_mode = (controller_mode >> 8) & 7; + u32 system_refresh_mode = (controller_mode >> 8) & 7;
// Code below assumes that most aggressive settings are in // force when we are called, either via E7501 reset defaults @@ -1493,9 +1495,9 @@ static void configure_e7501_dram_controller_mode(const struct
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
- uint32_t dimm_refresh_mode; + u32 dimm_refresh_mode; int value; - uint16_t dimm_socket_address; + u16 dimm_socket_address;
if (!(dimm_mask & (1 << i))) { continue; // This DIMM not usable @@ -1574,14 +1576,14 @@ static void configure_e7501_dram_controller_mode(const struct * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_row_attributes(const struct mem_controller - *ctrl, uint8_t dimm_mask) + *ctrl, u8 dimm_mask) { int i; - uint32_t row_attributes = 0; + u32 row_attributes = 0;
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- uint16_t dimm_socket_address = ctrl->channel0[i]; + u16 dimm_socket_address = ctrl->channel0[i]; struct dimm_size page_size; struct dimm_size sdram_width;
@@ -1622,14 +1624,14 @@ static void configure_e7501_row_attributes(const struct mem_controller * * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ -static void enable_e7501_clocks(uint8_t dimm_mask) +static void enable_e7501_clocks(u8 dimm_mask) { int i; - uint8_t clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS); + u8 clock_disable = pci_read_config8(PCI_DEV(0, 0, 0), CKDIS);
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- uint8_t socket_mask = 1 << i; + u8 socket_mask = 1 << i;
if (dimm_mask & socket_mask) clock_disable &= ~socket_mask; // DIMM present, enable clock @@ -1647,7 +1649,7 @@ static void enable_e7501_clocks(uint8_t dimm_mask) */ static void RAM_RESET_DDR_PTR(void) { - uint8_t byte; + u8 byte; byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); byte |= (1 << 4); pci_write_config8(PCI_DEV(0, 0, 0), 0x88, byte); @@ -1675,10 +1677,10 @@ static void ram_set_d0f0_regs(void)
for (i = 0; i < num_values; i += 3) {
- uint32_t register_offset = constant_register_values[i]; - uint32_t bits_to_mask = constant_register_values[i + 1]; - uint32_t bits_to_set = constant_register_values[i + 2]; - uint32_t register_value; + u32 register_offset = constant_register_values[i]; + u32 bits_to_mask = constant_register_values[i + 1]; + u32 bits_to_set = constant_register_values[i + 2]; + u32 register_value;
// It's theoretically possible to set values for something other than D0:F0, // but it's not typically done here @@ -1704,13 +1706,13 @@ static void ram_set_d0f0_regs(void) * @param src_addr TODO * @param dst_addr TODO */ -static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) +static void write_8dwords(const u32 *src_addr, u32 dst_addr) { int i; for (i = 0; i < 8; i++) { write32(dst_addr, *src_addr); src_addr++; - dst_addr += sizeof(uint32_t); + dst_addr += sizeof(u32); } }
@@ -1726,8 +1728,8 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) */ static void ram_set_rcomp_regs(void) { - uint32_t dword; - uint8_t maybe_strength_control; + u32 dword; + u8 maybe_strength_control;
RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
@@ -1843,8 +1845,8 @@ Public interface: static void sdram_enable(int controllers, const struct mem_controller *ctrl) { - uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD); - uint32_t dram_controller_mode; + u8 dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD); + u32 dram_controller_mode;
if (dimm_mask == 0) return; @@ -1954,7 +1956,7 @@ static void sdram_enable(int controllers, */ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { - uint8_t dimm_mask; + u8 dimm_mask;
RAM_DEBUG_MESSAGE("Reading SPD data...\n");
diff --git a/src/northbridge/intel/e7501/reset_test.c b/src/northbridge/intel/e7501/reset_test.c index 1c0dad5..d625d86 100644 --- a/src/northbridge/intel/e7501/reset_test.c +++ b/src/northbridge/intel/e7501/reset_test.c @@ -6,7 +6,7 @@ * has been enabled. */ static int bios_reset_detected(void) { - uint32_t dword; + u32 dword;
dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index 3d6ca2a..fe0a99f 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -29,7 +29,7 @@ void print_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -74,7 +74,7 @@ void dump_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -91,7 +91,7 @@ void dump_pci_devices_on_bus(unsigned busn) for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -236,7 +236,7 @@ void dump_io_resources(unsigned port) print_debug(":\n"); #endif for(i=0;i<256;i++) { - uint8_t val; + u8 val; if ((i & 0x0f) == 0) { #if !defined(__ROMCC__) printk(BIOS_DEBUG, "%02x:", i); diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08cd023..d2b9d84 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -19,7 +19,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + u32 pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; @@ -31,7 +31,7 @@ static void pci_domain_set_resources(device_t dev) * too confusing to get right. Kilobytes are good up to * 4 Terabytes of RAM... */ - uint16_t tolm_r, remapbase_r, remaplimit_r; + u16 tolm_r, remapbase_r, remaplimit_r; unsigned long tomk, tolmk; unsigned long remapbasek, remaplimitk; int idx; diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 909e740..bfc064e 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -70,7 +70,7 @@ struct dimm_size { unsigned long side2; };
-static const uint32_t refresh_frequency[] = { +static const u32 refresh_frequency[] = { /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) * 0 == least frequent refresh (longest interval between refreshes) @@ -86,7 +86,7 @@ static const uint32_t refresh_frequency[] = { 0, 2, 3, 1, 0, 0, 0, 4 };
-static const uint32_t refresh_rate_map[] = { +static const u32 refresh_rate_map[] = { /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode * Select values (array value) * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 @@ -102,11 +102,11 @@ static const uint32_t refresh_rate_map[] = { 1, 7, 2, 1, 1, 3 };
-#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) +#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(u32)) - 1)
#ifdef VALIDATE_DIMM_COMPATIBILITY // SPD parameters that must match for dual-channel operation -static const uint8_t dual_channel_parameters[] = { +static const u8 dual_channel_parameters[] = { SPD_MEMORY_TYPE, SPD_MODULE_VOLTAGE, SPD_NUM_COLUMNS, @@ -165,13 +165,13 @@ static const uint8_t dual_channel_parameters[] = {
/* DDR RECOMP tables */ // Slew table for 2x drive? -static const uint32_t slew_2x[] = { +static const u32 slew_2x[] = { 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff, };
// Pull Up / Pull Down offset table, if analogous to IXP2800? -static const uint32_t pull_updown_offset_table[] = { +static const u32 pull_updown_offset_table[] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x88888888, 0x88888888, 0x88888888, 0x88888888, }; @@ -234,7 +234,7 @@ typedef enum { */ static void mchtest_control(mchtst_cc cmd) { - uint32_t dword = pci_read_config32(MCHDEV, MCHTST); + u32 dword = pci_read_config32(MCHDEV, MCHTST); switch (cmd) { case MCHTST_CMD_0: dword &= ~(3 << 30); @@ -262,7 +262,7 @@ static void mchtest_control(mchtst_cc cmd) static void d060_control(d060_cc cmd) { mchtest_control(D060_ENABLE); - uint32_t dword = pci_read_config32(D060DEV, 0xf0); + u32 dword = pci_read_config32(D060DEV, 0xf0); switch (cmd) { case D060_CMD_0: dword |= (1 << 2); @@ -280,7 +280,7 @@ static void d060_control(d060_cc cmd) */ static void rcomp_smr_control(rcomp_smr_cc cmd) { - uint32_t dword = read32(RCOMP_MMIO + SMRCTL); + u32 dword = read32(RCOMP_MMIO + SMRCTL); switch (cmd) { case RCOMP_HOLD: dword |= (1 << 9); @@ -318,9 +318,9 @@ static void die_on_spd_error(int spd_return_value) * @param dimm_socket_address SMBus address of DIMM socket to interrogate. * @return log2(page size) for each side of the DIMM. */ -static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) +static struct dimm_size sdram_spd_get_page_size(u16 dimm_socket_address) { - uint16_t module_data_width; + u16 module_data_width; int value; struct dimm_size pgsz;
@@ -381,7 +381,7 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) * @param dimm_socket_address SMBus address of DIMM socket to interrogate. * @return Width in bits of each DIMM side's DRAMs. */ -static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) +static struct dimm_size sdram_spd_get_width(u16 dimm_socket_address) { int value; struct dimm_size width; @@ -482,11 +482,11 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) * @return 1 if both DIMM sockets report the same value for the specified * SPD parameter, 0 if the values differed or an error occurred. */ -static uint8_t are_spd_values_equal(uint8_t spd_byte_number, - uint16_t dimm0_address, - uint16_t dimm1_address) +static u8 are_spd_values_equal(u8 spd_byte_number, + u16 dimm0_address, + u16 dimm1_address) { - uint8_t bEqual = 0; + u8 bEqual = 0; int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
@@ -516,10 +516,10 @@ static uint8_t are_spd_values_equal(uint8_t spd_byte_number, * ... * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 */ -static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) +static u8 spd_get_supported_dimms(const struct mem_controller *ctrl) { int i; - uint8_t dimm_mask = 0; + u8 dimm_mask = 0;
// Have to increase size of dimm_mask if this assertion is violated ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4); @@ -530,9 +530,9 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- uint16_t channel0_dimm = ctrl->channel0[i]; - uint16_t channel1_dimm = ctrl->channel1[i]; - uint8_t bDualChannel = 1; + u16 channel0_dimm = ctrl->channel0[i]; + u16 channel1_dimm = ctrl->channel1[i]; + u8 bDualChannel = 1; #ifdef VALIDATE_DIMM_COMPATIBILITY struct dimm_size page_size; struct dimm_size sdram_width; @@ -662,12 +662,12 @@ SDRAM configuration functions: * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the * register value in JEDEC format. */ -static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) +static void do_ram_command(u8 command, u16 jedec_mode_bits) { - uint8_t dimm_start_64M_multiple; - uint32_t dimm_start_address; - uint32_t dram_controller_mode; - uint8_t i; + u8 dimm_start_64M_multiple; + u32 dimm_start_address; + u32 dram_controller_mode; + u8 i;
// Configure the RAM command dram_controller_mode = pci_read_config32(MCHDEV, DRC); @@ -708,7 +708,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) */ for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
- uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i); + u8 dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i);
if (dimm_end_64M_multiple > dimm_start_64M_multiple) { dimm_start_address &= 0x3ffffff; @@ -730,11 +730,11 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the * register value in JEDEC format. */ -static void set_ram_mode(uint16_t jedec_mode_bits) +static void set_ram_mode(u16 jedec_mode_bits) { ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
- uint32_t dram_cas_latency = + u32 dram_cas_latency = pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;
switch (dram_cas_latency) { @@ -770,7 +770,9 @@ DIMM-independant configuration functions: * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). * @return New multiple of 64 MB total DRAM in the system. */ -static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) +static u8 configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, + u8 total_dram_64M_multiple, + unsigned dimm_index) { int i;
@@ -834,10 +836,10 @@ static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ static void configure_e7501_ram_addresses(const struct mem_controller - *ctrl, uint8_t dimm_mask) + *ctrl, u8 dimm_mask) { int i; - uint8_t total_dram_64M_multiple = 0; + u8 total_dram_64M_multiple = 0;
// Configure the E7501's DRAM row boundaries // Start by zeroing out the temporary initial configuration @@ -846,7 +848,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- uint16_t dimm_socket_address = ctrl->channel0[i]; + u16 dimm_socket_address = ctrl->channel0[i]; struct dimm_size sz;
if (!(dimm_mask & (1 << i))) @@ -893,11 +895,11 @@ static void configure_e7501_ram_addresses(const struct mem_controller // Round up to 128MB granularity // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
- uint8_t total_dram_128M_multiple = + u8 total_dram_128M_multiple = (total_dram_64M_multiple + 1) >> 1;
// Convert to high 16 bits of address - uint16_t top_of_low_memory = + u16 top_of_low_memory = total_dram_128M_multiple << 11;
pci_write_config16(MCHDEV, TOLM, @@ -908,8 +910,8 @@ static void configure_e7501_ram_addresses(const struct mem_controller // > 3 GB total RAM
// Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory - uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0 - uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF + u16 remap_base = total_dram_64M_multiple; // A[25:0] == 0 + u16 remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF
// Put TOLM at 3 GB
@@ -942,7 +944,7 @@ static void configure_e7501_ram_addresses(const struct mem_controller static inline void __attribute__((always_inline)) initialize_ecc(unsigned long ret_addr, unsigned long ret_addr2) { - uint16_t scrubbed = pci_read_config16(MCHDEV, MCHCFGNS) & 0x08; + u16 scrubbed = pci_read_config16(MCHDEV, MCHCFGNS) & 0x08;
if (!scrubbed) { RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); @@ -1033,15 +1035,15 @@ static inline void __attribute__((always_inline)) * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, - uint8_t dimm_mask) + u8 dimm_mask) { int i; - uint32_t dram_timing; + u32 dram_timing; int value; - uint8_t slowest_row_precharge = 0; - uint8_t slowest_ras_cas_delay = 0; - uint8_t slowest_active_to_precharge_delay = 0; - uint32_t current_cas_latency = + u8 slowest_row_precharge = 0; + u8 slowest_ras_cas_delay = 0; + u8 slowest_active_to_precharge_delay = 0; + u32 current_cas_latency = pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;
// CAS# latency must be programmed beforehand @@ -1051,7 +1053,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, // Each timing parameter is determined by the slowest DIMM
for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - uint16_t dimm_socket_address; + u16 dimm_socket_address;
if (!(dimm_mask & (1 << i))) continue; // This DIMM not present @@ -1167,24 +1169,24 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, - uint8_t dimm_mask) + u8 dimm_mask) { int i; int value; - uint32_t dram_timing; - uint16_t dram_read_timing; - uint32_t dword; + u32 dram_timing; + u16 dram_read_timing; + u32 dword;
// CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format // NOTE: E7501 supports only 2.0 and 2.5 - uint32_t system_compatible_cas_latencies = + u32 system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; - uint32_t current_cas_latency; - uint32_t dimm_compatible_cas_latencies; + u32 current_cas_latency; + u32 dimm_compatible_cas_latencies;
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
- uint16_t dimm_socket_address; + u16 dimm_socket_address;
if (!(dimm_mask & (1 << i))) continue; // This DIMM not usable @@ -1266,7 +1268,7 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, dram_read_timing |= 0x0222; } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
- uint32_t dram_row_attributes = + u32 dram_row_attributes = pci_read_config32(MCHDEV, DRA);
dram_timing |= DRT_CAS_2_5; @@ -1324,14 +1326,14 @@ hw_err: */ static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl, - uint8_t dimm_mask) + u8 dimm_mask) { int i;
// Initial settings - uint32_t controller_mode = + u32 controller_mode = pci_read_config32(MCHDEV, DRC); - uint32_t system_refresh_mode = (controller_mode >> 8) & 7; + u32 system_refresh_mode = (controller_mode >> 8) & 7;
// Code below assumes that most aggressive settings are in // force when we are called, either via E7501 reset defaults @@ -1349,9 +1351,9 @@ static void configure_e7501_dram_controller_mode(const struct
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
- uint32_t dimm_refresh_mode; + u32 dimm_refresh_mode; int value; - uint16_t dimm_socket_address; + u16 dimm_socket_address;
if (!(dimm_mask & (1 << i))) { continue; // This DIMM not usable @@ -1430,14 +1432,14 @@ static void configure_e7501_dram_controller_mode(const struct * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). */ static void configure_e7501_row_attributes(const struct mem_controller - *ctrl, uint8_t dimm_mask) + *ctrl, u8 dimm_mask) { int i; - uint32_t row_attributes = 0; + u32 row_attributes = 0;
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- uint16_t dimm_socket_address = ctrl->channel0[i]; + u16 dimm_socket_address = ctrl->channel0[i]; struct dimm_size page_size; struct dimm_size sdram_width;
@@ -1478,16 +1480,16 @@ static void configure_e7501_row_attributes(const struct mem_controller * * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). */ -static void enable_e7501_clocks(uint8_t dimm_mask) +static void enable_e7501_clocks(u8 dimm_mask) { int i; - uint8_t clock_disable = pci_read_config8(MCHDEV, CKDIS); + u8 clock_disable = pci_read_config8(MCHDEV, CKDIS);
pci_write_config8(MCHDEV, 0x8e, 0xb0);
for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- uint8_t socket_mask = 1 << i; + u8 socket_mask = 1 << i;
if (dimm_mask & socket_mask) clock_disable &= ~socket_mask; // DIMM present, enable clock @@ -1505,7 +1507,7 @@ static void enable_e7501_clocks(uint8_t dimm_mask) */ static void RAM_RESET_DDR_PTR(void) { - uint8_t byte; + u8 byte; byte = pci_read_config8(MCHDEV, 0x88); byte |= (1 << 4); pci_write_config8(MCHDEV, 0x88, byte); @@ -1521,13 +1523,13 @@ static void RAM_RESET_DDR_PTR(void) * @param src_addr TODO * @param dst_addr TODO */ -static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) +static void write_8dwords(const u32 *src_addr, u32 dst_addr) { int i; for (i = 0; i < 8; i++) { write32(dst_addr, *src_addr); src_addr++; - dst_addr += sizeof(uint32_t); + dst_addr += sizeof(u32); } }
@@ -1543,8 +1545,8 @@ static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr) */ static void rcomp_copy_registers(void) { - uint32_t dword; - uint8_t strength_control; + u32 dword; + u8 strength_control;
RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
@@ -1635,7 +1637,7 @@ static void ram_set_rcomp_regs(void) d060_control(D060_CMD_0); mchtest_control(MCHTST_CMD_0);
- uint8_t revision = pci_read_config8(MCHDEV, 0x08); + u8 revision = pci_read_config8(MCHDEV, 0x08); if (revision >= 3) { rcomp_smr_control(RCOMP_SMR_00); rcomp_smr_control(RCOMP_SMR_01); @@ -1664,8 +1666,8 @@ Public interface: */ static void sdram_enable(const struct mem_controller *ctrl) { - uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD); - uint32_t dram_controller_mode; + u8 dimm_mask = pci_read_config16(MCHDEV, SKPD); + u32 dram_controller_mode;
if (dimm_mask == 0) return; @@ -1744,7 +1746,7 @@ static void sdram_enable(const struct mem_controller *ctrl) static void sdram_post_ecc(const struct mem_controller *ctrl) { /* Fast CS# Enable. */ - uint32_t dram_controller_mode = pci_read_config32(MCHDEV, DRC); + u32 dram_controller_mode = pci_read_config32(MCHDEV, DRC); dram_controller_mode = pci_read_config32(MCHDEV, DRC); dram_controller_mode |= (1 << 17); pci_write_config32(MCHDEV, DRC, dram_controller_mode); @@ -1760,7 +1762,7 @@ static void sdram_post_ecc(const struct mem_controller *ctrl) */ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { - uint8_t dimm_mask; + u8 dimm_mask;
RAM_DEBUG_MESSAGE("Reading SPD data...\n");
@@ -1921,6 +1923,6 @@ void e7505_mch_done(const struct mem_controller *memctrl)
int e7505_mch_is_ready(void) { - uint32_t dword = pci_read_config32(MCHDEV, DRC); + u32 dword = pci_read_config32(MCHDEV, DRC); return !!(dword & DRC_DONE); } diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index be3a3ac..7cac555 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -43,8 +43,8 @@ static int bridge_revision_id = -1; int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = pci_read_config16( + u8 stepping = cpuid_eax(1) & 0xf; + u8 bridge_id = pci_read_config16( dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a95d736..a890993 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -42,14 +42,14 @@ static int bridge_revision_id = -1; static u8 finished_FSP_after_pci = 0;
/* IGD UMA memory */ -static uint64_t uma_memory_base = 0; -static uint64_t uma_memory_size = 0; +static u64 uma_memory_base = 0; +static u64 uma_memory_size = 0;
int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = pci_read_config16( + u8 stepping = cpuid_eax(1) & 0xf; + u8 bridge_id = pci_read_config16( dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; @@ -123,9 +123,9 @@ static void add_fixed_resources(struct device *dev, int index)
static void pci_domain_set_resources(device_t dev) { - uint64_t tom, me_base, touud; - uint32_t tseg_base, uma_size, tolud; - uint16_t ggc; + u64 tom, me_base, touud; + u32 tseg_base, uma_size, tolud; + u16 ggc; unsigned long long tomk;
tomk = ggc = tseg_base = uma_size = tolud = tom = me_base = touud = 0; diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index fb40b94..aa8d360 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -6,7 +6,7 @@
static void bootblock_northbridge_init(void) { - uint32_t reg; + u32 reg;
/* * The "io" variant of the config access is explicitly used to diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74e16ad..c9cc442 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -240,8 +240,8 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, return; }
- link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + link_m1 = ((u64)link_n1 * edid.pixel_clock) / link_frequency; + data_m1 = ((u64)data_n1 * 18 * edid.pixel_clock) / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 743007e..02f5bc6 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -5,7 +5,7 @@
static void bootblock_northbridge_init(void) { - uint32_t reg; + u32 reg;
/* * The "io" variant of the config access is explicitly used to diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..b9d7da6 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -204,10 +204,10 @@ struct map_entry { };
static void read_map_entry(device_t dev, struct map_entry *entry, - uint64_t *result) + u64 *result) { - uint64_t value; - uint64_t mask; + u64 value; + u64 mask;
/* All registers are on a 1MiB granularity. */ mask = ((1ULL<<20)-1); @@ -272,7 +272,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), };
-static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(device_t dev, u64 *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -280,7 +280,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } }
-static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(device_t dev, u64 *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -297,7 +297,7 @@ static void mc_add_dram_resources(device_t dev) unsigned long touud_k; unsigned long index; struct resource *resource; - uint64_t mc_values[NUM_MAP_ENTRIES]; + u64 mc_values[NUM_MAP_ENTRIES];
/* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 4f5a989..7b3947e 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -714,7 +714,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) { u32 dimm; u32 edge; - int32_t data32; + s32 data32; u32 dcal_data32_0; u32 dcal_data32_1; u32 dcal_data32_2; @@ -722,7 +722,7 @@ static void set_receive_enable(const struct mem_controller *ctrl) u32 work32l; u32 work32h; u32 data32r; - int32_t recen; + s32 recen; for(dimm=0;dimm<8;dimm+=1) {
if(!(dimm&1)) { diff --git a/src/northbridge/intel/i3100/reset_test.c b/src/northbridge/intel/i3100/reset_test.c index de86f80..6e174ba 100644 --- a/src/northbridge/intel/i3100/reset_test.c +++ b/src/northbridge/intel/i3100/reset_test.c @@ -8,7 +8,7 @@ */ int bios_reset_detected(void) { - uint32_t dword; + u32 dword;
dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 12ff37b..2142dd8 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -35,7 +35,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { static void i440bx_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + u32 pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index e3cfbdf..2fd3926 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -61,7 +61,7 @@ Macros and definitions. * [4] == Extended(4x) 62.5 us -> 62.4 us * [5] == Extended(8x) 125 us -> 124.8 us */ -static const uint32_t refresh_rate_map[] = { +static const u32 refresh_rate_map[] = { 1, 5, 5, 2, 3, 4 };
@@ -446,13 +446,13 @@ static void set_dram_buffer_strength(void) * mbsc1 doubles as drb1 * mbfs0 doubles as i and reg */ - uint8_t mbsc0,mbsc1,mbsc3,mbsc4,mbfs0,mbfs2,fsb; + u8 mbsc0,mbsc1,mbsc3,mbsc4,mbfs0,mbfs2,fsb;
/* Tally how many rows between rows 0-3 and rows 4-7 are populated. * This determines how to program MBFS and MBSC. */ - uint8_t dimm03 = 0; - uint8_t dimm47 = 0; + u8 dimm03 = 0; + u8 dimm47 = 0;
mbsc0 = 0; for (mbfs0 = DRB0; mbfs0 <= DRB7; mbfs0++) { @@ -601,7 +601,7 @@ DIMM-independant configuration functions. static void spd_enable_refresh(void) { int i, value; - uint8_t reg; + u8 reg;
reg = pci_read_config8(NB, DRAMC);
@@ -624,7 +624,7 @@ Public interface. void sdram_set_registers(void) { int i, max; - uint8_t reg; + u8 reg;
PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index 60e62c1..1223328 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -61,7 +61,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { static void i440lx_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + u32 pci_tolm;
pci_tolm = find_pci_tolm(dev->link_list); mc_dev = dev->link_list->children; diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c index 7d283a1..6bacce9 100644 --- a/src/northbridge/intel/i440lx/raminit.c +++ b/src/northbridge/intel/i440lx/raminit.c @@ -187,7 +187,7 @@ DIMM-independant configuration functions.
static void spd_enable_refresh(void) { - uint8_t reg; + u8 reg;
reg = pci_read_config8(NB, DRAMC);
@@ -209,7 +209,7 @@ Public interface.
static void northbridge_init(void) { - uint32_t reg32; + u32 reg32;
reg32 = pci_read_config32(NB, APBASE); reg32 &= 0xe8000000U; @@ -255,7 +255,7 @@ static void sdram_set_registers(void)
/* Set registers as specified in the register_values[] array. */ for (i = 0; i < max; i += 3) { - uint8_t reg,tmp; + u8 reg,tmp; reg = pci_read_config8(NB, register_values[i]); reg &= register_values[i + 1]; reg |= register_values[i + 2] & ~(register_values[i + 1]); @@ -293,7 +293,7 @@ static void sdram_set_spd_registers(void) u16 memsize = 0;
for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t ds = 0; // dimm size + u16 ds = 0; // dimm size int j; /* this code skips second bank on each socket (no idea how to fix it now) */ diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index a9b3560..54a4dc4 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -43,8 +43,8 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void mc_read_resources(device_t dev) { struct resource *resource; - uint32_t hecbase, amsize, tolm; - uint64_t ambase, memsize; + u32 hecbase, amsize, tolm; + u64 ambase, memsize; int idx = 0;
device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0)); @@ -83,14 +83,14 @@ static void mc_read_resources(device_t dev) if (hecbase) { printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28); resource = new_resource(dev, idx++); - resource->base = (resource_t)(uint64_t)hecbase << 28; + resource->base = (resource_t)(u64)hecbase << 28; resource->size = (resource_t)256 * 1024 * 1024; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
resource = new_resource(dev, idx++); - resource->base = (resource_t)(uint64_t)0xffe00000; + resource->base = (resource_t)(u64)0xffe00000; resource->size = (resource_t)0x200000; resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index ce0dc20..bc95261 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -73,7 +73,7 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; int igd_memory = 0; - uint64_t uma_memory_base = 0, uma_memory_size = 0; + u64 uma_memory_base = 0, uma_memory_size = 0;
mc_dev = dev->link_list->children; if (!mc_dev) diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 4898aaf..f7b06b4 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -54,7 +54,7 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; int igd_memory = 0; - uint64_t uma_memory_base = 0, uma_memory_size = 0; + u64 uma_memory_base = 0, uma_memory_size = 0;
mc_dev = dev->link_list->children; if (!mc_dev) diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c index 327f47d..4709700 100644 --- a/src/northbridge/intel/i855/debug.c +++ b/src/northbridge/intel/i855/debug.c @@ -36,7 +36,7 @@ static inline void print_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -75,7 +75,7 @@ static inline void dump_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index fce7d57..e449ca3 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -55,7 +55,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + u32 pci_tolm;
printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor); printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device); diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 0ab4d38..23ea631 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -69,7 +69,7 @@ struct dimm_size { unsigned int side2; };
-static const uint32_t refresh_frequency[] = { +static const u32 refresh_frequency[] = { /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) * 0 == least frequent refresh (longest interval between refreshes) @@ -85,7 +85,7 @@ static const uint32_t refresh_frequency[] = { 0, 2, 3, 1, 0, 0, 0, 4 };
-static const uint32_t refresh_rate_map[] = { +static const u32 refresh_rate_map[] = { /* Map the JEDEC spd refresh rates (array index) to i855 Refresh Mode * Select values (array value) * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 @@ -101,7 +101,7 @@ static const uint32_t refresh_rate_map[] = { 1, 7, 2, 1, 1, 1 };
-#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) +#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(u32)) - 1)
/*----------------------------------------------------------------------------- SPD functions: @@ -129,7 +129,7 @@ static void die_on_spd_error(int spd_return_value) */ static struct dimm_size sdram_spd_get_page_size(u8 dimm_socket_address) { - uint16_t module_data_width; + u16 module_data_width; int value; struct dimm_size pgsz;
@@ -276,10 +276,10 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm) * * @return A bitmask indicating which sockets contain a compatible DIMM. */ -static uint8_t spd_get_supported_dimms(void) +static u8 spd_get_supported_dimms(void) { int i; - uint8_t dimm_mask = 0; + u8 dimm_mask = 0;
for (i = 0; i < DIMM_SOCKETS; i++) { u8 dimm = DIMM0 + i; @@ -358,12 +358,12 @@ static uint8_t spd_get_supported_dimms(void) SDRAM configuration functions: -----------------------------------------------------------------------------*/
-static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) +static void do_ram_command(u8 command, u16 jedec_mode_bits) { int i; u32 reg32; - uint8_t dimm_start_32M_multiple = 0; - uint16_t i855_mode_bits = jedec_mode_bits; + u8 dimm_start_32M_multiple = 0; + u16 i855_mode_bits = jedec_mode_bits;
/* Configure the RAM command. */ reg32 = pci_read_config32(NORTHBRIDGE_MMC, DRC); @@ -388,10 +388,10 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) }
for (i = 0; i < (DIMM_SOCKETS * 2); ++i) { - uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i); + u8 dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i); if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
- uint32_t dimm_start_address = dimm_start_32M_multiple << 25; + u32 dimm_start_address = dimm_start_32M_multiple << 25; PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits); read32(dimm_start_address + i855_mode_bits);
@@ -404,7 +404,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
static void set_initialize_complete(void) { - uint32_t drc_reg; + u32 drc_reg;
drc_reg = pci_read_config32(NORTHBRIDGE_MMC, DRC); drc_reg |= (1 << 29); @@ -502,10 +502,10 @@ static void sdram_set_registers(void) */ }
-static void spd_set_row_attributes(uint8_t dimm_mask) +static void spd_set_row_attributes(u8 dimm_mask) { int i; - uint16_t row_attributes = 0; + u16 row_attributes = 0;
for (i = 0; i < DIMM_SOCKETS; i++) { u8 dimm = DIMM0 + i; @@ -539,7 +539,7 @@ static void spd_set_row_attributes(uint8_t dimm_mask) pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes); }
-static void spd_set_dram_controller_mode(uint8_t dimm_mask) +static void spd_set_dram_controller_mode(u8 dimm_mask) { int i;
@@ -554,7 +554,7 @@ static void spd_set_dram_controller_mode(uint8_t dimm_mask)
for (i = 0; i < DIMM_SOCKETS; i++) { u8 dimm = DIMM0 + i; - uint32_t dimm_refresh_mode; + u32 dimm_refresh_mode; int value; u8 tRCD, tRP;
@@ -605,23 +605,23 @@ static void spd_set_dram_controller_mode(uint8_t dimm_mask) pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode); }
-static void spd_set_dram_timing(uint8_t dimm_mask) +static void spd_set_dram_timing(u8 dimm_mask) { int i; u32 dram_timing;
// CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format // NOTE: i82822 supports only 2.0 and 2.5 - uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; - uint8_t slowest_row_precharge = 0; - uint8_t slowest_ras_cas_delay = 0; - uint8_t slowest_active_to_precharge_delay = 0; + u32 system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; + u8 slowest_row_precharge = 0; + u8 slowest_ras_cas_delay = 0; + u8 slowest_active_to_precharge_delay = 0;
for (i = 0; i < DIMM_SOCKETS; i++) { u8 dimm = DIMM0 + i; int value; - uint32_t current_cas_latency; - uint32_t dimm_compatible_cas_latencies; + u32 current_cas_latency; + u32 dimm_compatible_cas_latencies; if (!(dimm_mask & (1 << i))) continue; // This DIMM not usable
@@ -703,7 +703,7 @@ static void spd_set_dram_timing(uint8_t dimm_mask) } else die("No CAS# latencies compatible with all DIMMs!!\n");
- uint32_t current_cas_latency = dram_timing & DRT_CAS_MASK; + u32 current_cas_latency = dram_timing & DRT_CAS_MASK;
/* tRP */
@@ -783,11 +783,11 @@ static void spd_set_dram_timing(uint8_t dimm_mask) pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing); }
-static void spd_set_dram_size(uint8_t dimm_mask) +static void spd_set_dram_size(u8 dimm_mask) { int i; int total_dram = 0; - uint32_t drb_reg = 0; + u32 drb_reg = 0;
for (i = 0; i < DIMM_SOCKETS; i++) { u8 dimm = DIMM0 + i; @@ -815,7 +815,7 @@ static void spd_set_dram_size(uint8_t dimm_mask)
static void spd_set_dram_pwr_management(void) { - uint32_t pwrmg_reg; + u32 pwrmg_reg;
pwrmg_reg = 0x10f10430; pci_write_config32(NORTHBRIDGE_MMC, PWRMG, pwrmg_reg); @@ -823,7 +823,7 @@ static void spd_set_dram_pwr_management(void)
static void spd_set_dram_throttle_control(void) { - uint32_t dtc_reg = 0; + u32 dtc_reg = 0;
/* DDR SDRAM Throttle Mode (TMODE): * 0011 = Both Rank and GMCH Thermal Sensor based throttling is enabled. When the external SO- @@ -958,7 +958,7 @@ static void northbridge_set_registers(void)
static void sdram_set_spd_registers(void) { - uint8_t dimm_mask; + u8 dimm_mask;
PRINTK_DEBUG("Reading SPD data...\n");
diff --git a/src/northbridge/intel/i855/reset_test.c b/src/northbridge/intel/i855/reset_test.c index 513eba3..19595c0 100644 --- a/src/northbridge/intel/i855/reset_test.c +++ b/src/northbridge/intel/i855/reset_test.c @@ -27,7 +27,7 @@ */ static int bios_reset_detected(void) { - uint32_t dword; + u32 dword;
dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 4571446..55f85e6 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -5,7 +5,7 @@
static void bootblock_northbridge_init(void) { - uint32_t reg; + u32 reg;
/* * The "io" variant of the config access is explicitly used to diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index e47f762..9223a95 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -32,7 +32,7 @@ void print_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || @@ -70,7 +70,7 @@ void dump_pci_devices(void) for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { - uint32_t id; + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1aaeb3b..d3e0ec3 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -83,12 +83,12 @@ static void add_fixed_resources(struct device *dev, int index)
static void pci_domain_set_resources(device_t dev) { - uint32_t pci_tolm; - uint8_t tolud, reg8; - uint16_t reg16; + u32 pci_tolm; + u8 tolud, reg8; + u16 reg16; unsigned long long tomk, tomk_stolen; - uint64_t uma_memory_base = 0, uma_memory_size = 0; - uint64_t tseg_memory_base = 0, tseg_memory_size = 0; + u64 uma_memory_base = 0, uma_memory_size = 0; + u64 tseg_memory_base = 0, tseg_memory_size = 0;
/* Can we find out how much memory we can use at most * this way? @@ -158,8 +158,8 @@ static void pci_domain_set_resources(device_t dev) /* The following needs to be 2 lines, otherwise the second * number is always 0 */ - printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk_stolen); - printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen >> 10)); + printk(BIOS_INFO, "Available memory: %dK", (u32)tomk_stolen); + printk(BIOS_INFO, " (%dM)\n", (u32)(tomk_stolen >> 10));
/* Report the memory regions */ ram_resource(dev, 3, 0, 640); diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index c3e2a49..273af14 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -788,8 +788,8 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, return; }
- link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + link_m1 = ((u64)link_n1 * edid.pixel_clock) / link_frequency; + data_m1 = ((u64)data_n1 * 18 * edid.pixel_clock) / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 11d335a..27fd40b 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -43,8 +43,8 @@ static int bridge_revision_id = -1; int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = + u8 stepping = cpuid_eax(1) & 0xf; + u8 bridge_id = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; @@ -116,9 +116,9 @@ static struct device_operations pci_domain_ops = {
static void mc_read_resources(device_t dev) { - uint32_t tseg_base; - uint64_t TOUUD; - uint16_t reg16; + u32 tseg_base; + u64 TOUUD; + u16 reg16;
pci_dev_read_resources(dev);
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 1c1d492..fbeba0c 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -5,7 +5,7 @@
static void bootblock_northbridge_init(void) { - uint32_t reg; + u32 reg;
/* * The "io" variant of the config access is explicitly used to diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index e3e1f4b..0e4c042 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -308,9 +308,9 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 link_m1; u32 link_n1 = 0x00080000;
- link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; + link_m1 = ((u64)link_n1 * edid.pixel_clock) / link_frequency;
- data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + data_m1 = ((u64)data_n1 * 18 * edid.pixel_clock) / (link_frequency * 8 * (info->lvds_num_lanes ? : 1));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index 08cceea..bdcdb22 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -272,8 +272,8 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, return 0; }
- link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + link_m1 = ((u64)link_n1 * edid.pixel_clock) / link_frequency; + data_m1 = ((u64)data_n1 * 18 * edid.pixel_clock) / (link_frequency * 8 * (info->lvds_num_lanes ? : 4));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 55395ea..48dd45f 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -40,14 +40,14 @@ static int bridge_revision_id = -1;
/* IGD UMA memory */ -static uint64_t uma_memory_base = 0; -static uint64_t uma_memory_size = 0; +static u64 uma_memory_base = 0; +static u64 uma_memory_size = 0;
int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { - uint8_t stepping = cpuid_eax(1) & 0xf; - uint8_t bridge_id = pci_read_config16( + u8 stepping = cpuid_eax(1) & 0xf; + u8 bridge_id = pci_read_config16( dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; @@ -134,9 +134,9 @@ static void add_fixed_resources(struct device *dev, int index)
static void pci_domain_set_resources(device_t dev) { - uint64_t tom, me_base, touud; - uint32_t tseg_base, uma_size, tolud; - uint16_t ggc; + u64 tom, me_base, touud; + u32 tseg_base, uma_size, tolud; + u16 ggc; unsigned long long tomk;
/* Total Memory 2GB example: diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index de6dac7..a551717 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -906,7 +906,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) size_t tsegsize, mmiosize, toludbase, touudbase, gfxstolenbase, gttbase, tsegbase, mestolenbase; size_t tsegbasedelta, remapbase, remaplimit; - uint16_t ggc; + u16 ggc;
mmiosize = 0x400;
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index c552879..19d5ffa 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -99,8 +99,8 @@ static void pci_domain_set_resources(device_t dev) u8 reg8; u16 reg16; unsigned long long tomk, tolud, tomk_stolen; - uint64_t uma_memory_base = 0, uma_memory_size = 0; - uint64_t tseg_memory_base = 0, tseg_memory_size = 0; + u64 uma_memory_base = 0, uma_memory_size = 0; + u64 tseg_memory_base = 0, tseg_memory_size = 0;
/* Can we find out how much memory we can use at most this way? */ pci_tolm = find_pci_tolm(dev->link_list); diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c index b3ebde1..40e3abc 100644 --- a/src/northbridge/via/vx800/early_serial.c +++ b/src/northbridge/via/vx800/early_serial.c @@ -27,24 +27,24 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1
-static void vx800_writepnpaddr(uint8_t val) +static void vx800_writepnpaddr(u8 val) { outb(val, 0x2e); outb(val, 0xeb); }
-static void vx800_writepnpdata(uint8_t val) +static void vx800_writepnpdata(u8 val) { outb(val, 0x2f); outb(val, 0xeb); }
-static void vx800_writesiobyte(uint16_t reg, uint8_t val) +static void vx800_writesiobyte(u16 reg, u8 val) { outb(val, reg); }
-static void vx800_writesioword(uint16_t reg, uint16_t val) +static void vx800_writesioword(u16 reg, u16 val) { outw(val, reg); } diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index c96511e..1a15727 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -72,7 +72,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { device_t dev; - uint16_t values; + u16 values;
print_debug("In enable_mainboard_devices \n");
@@ -83,7 +83,7 @@ static void enable_mainboard_devices(void)
static void enable_shadow_ram(void) { - uint8_t shadowreg; + u8 shadowreg;
pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); /* 0xf0000-0xfffff - ACPI tables */ diff --git a/src/northbridge/via/vx800/translator_ddr2_init.c b/src/northbridge/via/vx800/translator_ddr2_init.c index 2bc7610..4073d70 100644 --- a/src/northbridge/via/vx800/translator_ddr2_init.c +++ b/src/northbridge/via/vx800/translator_ddr2_init.c @@ -24,10 +24,10 @@ #define TRUE 1 #define FALSE 0
-typedef int8_t INT8; +typedef s8 INT8; typedef unsigned long uintn_t; typedef uintn_t UINTN; typedef long intn_t; typedef intn_t INTN; typedef UINTN CB_STATUS; -typedef uint8_t BOOLEAN; +typedef u8 BOOLEAN; diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c index 4ee249f..0104058 100644 --- a/src/northbridge/via/vx800/vga.c +++ b/src/northbridge/via/vx800/vga.c @@ -161,7 +161,7 @@ static void vga_enable_console(void) extern u8 acpi_sleep_type; static void vga_init(device_t dev) { - uint8_t reg8; + u8 reg8;
mainboard_interrupt_handlers(0x15, &via_vx800_int15_handler);
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index fc9a202..914159f 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -280,7 +280,7 @@ static void chrome9hd_biosguide_init_seq(device_t dev)
chrome9hd_handle_uma(dev);
- uint64_t gfx_base = get_uma_memory_base(); + u64 gfx_base = get_uma_memory_base(); if (gfx_base == 0) die("uma_memory_base not set. Abandon ship!\n");
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index f9c225d..4092442 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -32,8 +32,8 @@
#define RAM_4GB (((u64)1) << 32)
-static uint64_t uma_memory_base = 0; -static uint64_t uma_memory_size = 0; +static u64 uma_memory_base = 0; +static u64 uma_memory_size = 0;
/** * @file northbridge.c @@ -51,7 +51,7 @@ void hard_reset(void) outb((1 << 2) | (1 << 1), 0xcf9); }
-uint64_t get_uma_memory_base(void) +u64 get_uma_memory_base(void) { printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, uma_memory_base >> 20); diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index 18d4c11..253b00a 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -39,27 +39,27 @@ void dump_pci_device(device_t dev) }
void pci_mod_config8(device_t dev, unsigned int where, - uint8_t clr_mask, uint8_t set_mask) + u8 clr_mask, u8 set_mask) { - uint8_t reg8 = pci_read_config8(dev, where); + u8 reg8 = pci_read_config8(dev, where); reg8 &= ~clr_mask; reg8 |= set_mask; pci_write_config8(dev, where, reg8); }
void pci_mod_config16(device_t dev, unsigned int where, - uint16_t clr_mask, uint16_t set_mask) + u16 clr_mask, u16 set_mask) { - uint16_t reg16 = pci_read_config16(dev, where); + u16 reg16 = pci_read_config16(dev, where); reg16 &= ~clr_mask; reg16 |= set_mask; pci_write_config16(dev, where, reg16); }
void pci_mod_config32(device_t dev, unsigned int where, - uint32_t clr_mask, uint32_t set_mask) + u32 clr_mask, u32 set_mask) { - uint32_t reg32 = pci_read_config32(dev, where); + u32 reg32 = pci_read_config32(dev, where); reg32 &= ~clr_mask; reg32 |= set_mask; pci_write_config32(dev, where, reg32); diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index aae0c99..02ec16e 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -177,7 +177,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
void acpi_fill_in_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const u16 pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; @@ -492,7 +492,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci_irq = acpi_sci_irq(); acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + u16 sci_flags = MP_IRQ_TRIGGER_LEVEL;
/* INT_SRC_OVR */ irqovr = (void *)current; diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index fa0d9ee..575018d 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -24,7 +24,7 @@ #include <baytrail/iosf.h> #include <cpu/intel/microcode/microcode.c>
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +static void set_var_mtrr(int reg, u32 base, u32 size, int type) { msr_t basem, maskm; basem.lo = base | type; @@ -52,7 +52,7 @@ static void enable_rom_caching(void)
static void setup_mmconfig(void) { - uint32_t reg; + u32 reg;
/* Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e8f95ae..2f2b656 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -83,7 +83,7 @@ void baytrail_init_cpus(device_t dev) struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); struct mp_params mp_params; - uint32_t bsmrwac; + u32 bsmrwac; void *default_smm_area;
/* Set up MTRRs based on physical address size. */ @@ -160,9 +160,9 @@ static const struct cpu_driver driver __cpu_driver = { */
struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; + u32 smbase; + u32 smrr_base; + u32 smrr_mask; };
static struct smm_relocation_attrs relo_attrs; @@ -257,11 +257,11 @@ static int install_permanent_handler(int num_cpus) static int smm_load_handlers(void) { /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); + const u32 rmask = ~((1 << 12) - 1); const struct pattrs *pattrs = pattrs_get();
/* Initialize global tracking state. */ - relo_attrs.smbase = (uint32_t)smm_region_start(); + relo_attrs.smbase = (u32)smm_region_start(); relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; relo_attrs.smrr_mask |= MTRRphysMaskValid; diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index df907a7..587cd4e 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -65,11 +65,11 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
static void log_wake_events(const struct chipset_power_state *ps) { - const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | + const u32 pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | PCIE_WAKE2_STS | PCIE_WAKE1_STS | PCIE_WAKE0_STS; - uint32_t gpe0_sts; - uint32_t gpio_mask; + u32 gpe0_sts; + u32 gpio_mask; int i;
/* Mask off disabled events. */ diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 4cce877..d9f5603 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -290,7 +290,7 @@ static void gfx_post_vbios_init(device_t dev) gfx_run_script(dev, gfx_post_vbios_script); }
-static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz) +static void set_backlight_pwm(device_t dev, u32 bklt_reg, int req_hz) { int divider; struct resource *res; diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 43e52ef..a2c15c8 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -175,7 +175,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios, static void setup_gpio_route(const struct soc_gpio_map *sus, const struct soc_gpio_map *core) { - uint32_t route_reg = 0; + u32 route_reg = 0; int i;
for (i = 0; i < 8; i++) { diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654..793632c 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -53,7 +53,7 @@ static const struct reg_script init_ops[] = { REG_SCRIPT_END, };
-static const uint32_t hdmi_codec_verb_table[] = { +static const u32 hdmi_codec_verb_table[] = { /* coreboot specific header */ 0x80862882, /* vid did for hdmi codec */ 0x00000000, /* subsystem id */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 2b07e2b..420088d 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -23,27 +23,27 @@ #if !defined(__PRE_RAM__) #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
-static inline void write_iosf_reg(int reg, uint32_t value) +static inline void write_iosf_reg(int reg, u32 value) { write32(IOSF_PCI_BASE + reg, value); } -static inline uint32_t read_iosf_reg(int reg) +static inline u32 read_iosf_reg(int reg) { return read32(IOSF_PCI_BASE + reg); } #else -static inline void write_iosf_reg(int reg, uint32_t value) +static inline void write_iosf_reg(int reg, u32 value) { pci_write_config32(IOSF_PCI_DEV, reg, value); } -static inline uint32_t read_iosf_reg(int reg) +static inline u32 read_iosf_reg(int reg) { return pci_read_config32(IOSF_PCI_DEV, reg); } #endif
/* Common sequences for all the port accesses. */ -static uint32_t iosf_read_port(uint32_t cr, int reg) +static u32 iosf_read_port(u32 cr, int reg) { cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); @@ -51,7 +51,7 @@ static uint32_t iosf_read_port(uint32_t cr, int reg) return read_iosf_reg(MDR_REG); }
-static void iosf_write_port(uint32_t cr, int reg, uint32_t val) +static void iosf_write_port(u32 cr, int reg, u32 val) { cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); @@ -64,224 +64,224 @@ static void iosf_write_port(uint32_t cr, int reg, uint32_t val) #define IOSF_WRITE(port) \ IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port)
-uint32_t iosf_bunit_read(int reg) +u32 iosf_bunit_read(int reg) { return iosf_read_port(IOSF_READ(BUNIT), reg); }
-void iosf_bunit_write(int reg, uint32_t val) +void iosf_bunit_write(int reg, u32 val) { iosf_write_port(IOSF_WRITE(BUNIT), reg, val); }
-uint32_t iosf_dunit_read(int reg) +u32 iosf_dunit_read(int reg) { return iosf_read_port(IOSF_READ(SYSMEMC), reg); }
-uint32_t iosf_dunit_ch0_read(int reg) +u32 iosf_dunit_ch0_read(int reg) { return iosf_dunit_read(reg); }
-uint32_t iosf_dunit_ch1_read(int reg) +u32 iosf_dunit_ch1_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | + u32 cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | IOSF_PORT(IOSF_PORT_DUNIT_CH1); return iosf_read_port(cr, reg); }
-void iosf_dunit_write(int reg, uint32_t val) +void iosf_dunit_write(int reg, u32 val) { iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); }
-uint32_t iosf_punit_read(int reg) +u32 iosf_punit_read(int reg) { return iosf_read_port(IOSF_READ(PMC), reg); }
-void iosf_punit_write(int reg, uint32_t val) +void iosf_punit_write(int reg, u32 val) { iosf_write_port(IOSF_WRITE(PMC), reg, val); }
-uint32_t iosf_usbphy_read(int reg) +u32 iosf_usbphy_read(int reg) { return iosf_read_port(IOSF_READ(USBPHY), reg); }
-void iosf_usbphy_write(int reg, uint32_t val) +void iosf_usbphy_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); }
-uint32_t iosf_ushphy_read(int reg) +u32 iosf_ushphy_read(int reg) { return iosf_read_port(IOSF_READ(USHPHY), reg); }
-void iosf_ushphy_write(int reg, uint32_t val) +void iosf_ushphy_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); }
-uint32_t iosf_lpss_read(int reg) +u32 iosf_lpss_read(int reg) { return iosf_read_port(IOSF_READ(LPSS), reg); }
-void iosf_lpss_write(int reg, uint32_t val) +void iosf_lpss_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(LPSS), reg, val); }
-uint32_t iosf_ccu_read(int reg) +u32 iosf_ccu_read(int reg) { return iosf_read_port(IOSF_READ(CCU), reg); }
-void iosf_ccu_write(int reg, uint32_t val) +void iosf_ccu_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(CCU), reg, val); }
-uint32_t iosf_score_read(int reg) +u32 iosf_score_read(int reg) { return iosf_read_port(IOSF_READ(SCORE), reg); }
-void iosf_score_write(int reg, uint32_t val) +void iosf_score_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(SCORE), reg, val); }
-uint32_t iosf_scc_read(int reg) +u32 iosf_scc_read(int reg) { return iosf_read_port(IOSF_READ(SCC), reg); }
-void iosf_scc_write(int reg, uint32_t val) +void iosf_scc_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(SCC), reg, val); }
-uint32_t iosf_aunit_read(int reg) +u32 iosf_aunit_read(int reg) { return iosf_read_port(IOSF_READ(AUNIT), reg); }
-void iosf_aunit_write(int reg, uint32_t val) +void iosf_aunit_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); }
-uint32_t iosf_cpu_bus_read(int reg) +u32 iosf_cpu_bus_read(int reg) { return iosf_read_port(IOSF_READ(CPU_BUS), reg); }
-void iosf_cpu_bus_write(int reg, uint32_t val) +void iosf_cpu_bus_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); }
-uint32_t iosf_sec_read(int reg) +u32 iosf_sec_read(int reg) { return iosf_read_port(IOSF_READ(SEC), reg); }
-void iosf_sec_write(int reg, uint32_t val) +void iosf_sec_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(SEC), reg, val); }
-uint32_t iosf_port45_read(int reg) +u32 iosf_port45_read(int reg) { return iosf_read_port(IOSF_READ(0x45), reg); }
-void iosf_port45_write(int reg, uint32_t val) +void iosf_port45_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(0x45), reg, val); }
-uint32_t iosf_port46_read(int reg) +u32 iosf_port46_read(int reg) { return iosf_read_port(IOSF_READ(0x46), reg); }
-void iosf_port46_write(int reg, uint32_t val) +void iosf_port46_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(0x46), reg, val); }
-uint32_t iosf_port47_read(int reg) +u32 iosf_port47_read(int reg) { return iosf_read_port(IOSF_READ(0x47), reg); }
-void iosf_port47_write(int reg, uint32_t val) +void iosf_port47_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(0x47), reg, val); }
-uint32_t iosf_port55_read(int reg) +u32 iosf_port55_read(int reg) { return iosf_read_port(IOSF_READ(0x55), reg); }
-void iosf_port55_write(int reg, uint32_t val) +void iosf_port55_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(0x55), reg, val); }
-uint32_t iosf_port58_read(int reg) +u32 iosf_port58_read(int reg) { return iosf_read_port(IOSF_READ(0x58), reg); }
-void iosf_port58_write(int reg, uint32_t val) +void iosf_port58_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(0x58), reg, val); }
-uint32_t iosf_port59_read(int reg) +u32 iosf_port59_read(int reg) { return iosf_read_port(IOSF_READ(0x59), reg); }
-void iosf_port59_write(int reg, uint32_t val) +void iosf_port59_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(0x59), reg, val); }
-uint32_t iosf_port5a_read(int reg) +u32 iosf_port5a_read(int reg) { return iosf_read_port(IOSF_READ(0x5a), reg); }
-void iosf_port5a_write(int reg, uint32_t val) +void iosf_port5a_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(0x5a), reg, val); }
-uint32_t iosf_porta2_read(int reg) +u32 iosf_porta2_read(int reg) { return iosf_read_port(IOSF_READ(0xa2), reg); }
-void iosf_porta2_write(int reg, uint32_t val) +void iosf_porta2_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(0xa2), reg, val); }
-uint32_t iosf_ssus_read(int reg) +u32 iosf_ssus_read(int reg) { return iosf_read_port(IOSF_READ(SSUS), reg); }
-void iosf_ssus_write(int reg, uint32_t val) +void iosf_ssus_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(SSUS), reg, val); } diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42b..00949b5 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -89,7 +89,7 @@ static void lpe_enable_acpi_mode(device_t dev)
static void setup_codec_clock(device_t dev) { - uint32_t reg; + u32 reg; int clk_reg; struct soc_intel_baytrail_config *config; const char *freq_str; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 8ff9712..187f83d 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -66,7 +66,7 @@ */ #define RES_IN_KiB(r) ((r) >> 10)
-uint32_t nc_read_top_of_low_memory(void) +u32 nc_read_top_of_low_memory(void) { return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); } diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 71b90de..964e76a 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -32,7 +32,7 @@ #include "chip.h"
static int pll_en_off; -static uint32_t strpfusecfg; +static u32 strpfusecfg;
static inline int root_port_offset(device_t dev) { @@ -112,7 +112,7 @@ static void byt_pcie_init(device_t dev)
if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; - uint32_t reg = pci_read_config32(dev, RPPGEN); + u32 reg = pci_read_config32(dev, RPPGEN); reg |= SRDLCGEN | SRDBCGEN;
if (config && config->clkreq_enable) @@ -176,7 +176,7 @@ static void byt_pcie_enable(device_t dev) { if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; - uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); + u32 reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); pll_en_off = !!(reg & PLL_OFF_EN);
strpfusecfg = pci_read_config32(dev, STRPFUSECFG); @@ -196,7 +196,7 @@ static void byt_pcie_enable(device_t dev)
static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) { - uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); + u32 didvid = ((did & 0xffff) << 16) | (vid & 0xffff);
if (!didvid) didvid = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee3726..b0f746c 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -48,12 +48,12 @@ static device_t get_pcu_dev(void) } #endif
-uint16_t get_pmbase(void) +u16 get_pmbase(void) { return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; }
-static void print_num_status_bits(int num_bits, uint32_t status, +static void print_num_status_bits(int num_bits, u32 status, const char *bit_names[]) { int i; @@ -71,12 +71,12 @@ static void print_num_status_bits(int num_bits, uint32_t status, } }
-static void print_status_bits(uint32_t status, const char *bit_names[]) +static void print_status_bits(u32 status, const char *bit_names[]) { print_num_status_bits(32, status, bit_names); }
-static uint32_t print_smi_status(uint32_t smi_sts) +static u32 print_smi_status(u32 smi_sts) { static const char *smi_sts_bits[] = { [2] = "BIOS", @@ -108,60 +108,60 @@ static uint32_t print_smi_status(uint32_t smi_sts) return smi_sts; }
-static uint32_t reset_smi_status(void) +static u32 reset_smi_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl(pmbase + SMI_STS); + u16 pmbase = get_pmbase(); + u32 smi_sts = inl(pmbase + SMI_STS); outl(smi_sts, pmbase + SMI_STS); return smi_sts; }
-uint32_t clear_smi_status(void) +u32 clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
-void enable_smi(uint32_t mask) +void enable_smi(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); + u16 pmbase = get_pmbase(); + u32 smi_en = inl(pmbase + SMI_EN); smi_en |= mask; outl(smi_en, pmbase + SMI_EN); }
-void disable_smi(uint32_t mask) +void disable_smi(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); + u16 pmbase = get_pmbase(); + u32 smi_en = inl(pmbase + SMI_EN); smi_en &= ~mask; outl(smi_en, pmbase + SMI_EN); }
-void enable_pm1_control(uint32_t mask) +void enable_pm1_control(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); + u16 pmbase = get_pmbase(); + u32 pm1_cnt = inl(pmbase + PM1_CNT); pm1_cnt |= mask; outl(pm1_cnt, pmbase + PM1_CNT); }
-void disable_pm1_control(uint32_t mask) +void disable_pm1_control(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); + u16 pmbase = get_pmbase(); + u32 pm1_cnt = inl(pmbase + PM1_CNT); pm1_cnt &= ~mask; outl(pm1_cnt, pmbase + PM1_CNT); }
-static uint16_t reset_pm1_status(void) +static u16 reset_pm1_status(void) { - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw(pmbase + PM1_STS); + u16 pmbase = get_pmbase(); + u16 pm1_sts = inw(pmbase + PM1_STS); outw(pm1_sts, pmbase + PM1_STS); return pm1_sts; }
-static uint16_t print_pm1_status(uint16_t pm1_sts) +static u16 print_pm1_status(u16 pm1_sts) { static const char *pm1_sts_bits[] = { [0] = "TMROF", @@ -184,17 +184,17 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) return pm1_sts; }
-uint16_t clear_pm1_status(void) +u16 clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); }
-void enable_pm1(uint16_t events) +void enable_pm1(u16 events) { outw(events, get_pmbase() + PM1_EN); }
-static uint32_t print_tco_status(uint32_t tco_sts) +static u32 print_tco_status(u32 tco_sts) { static const char *tco_sts_bits[] = { [3] = "TIMEOUT", @@ -211,33 +211,33 @@ static uint32_t print_tco_status(uint32_t tco_sts) return tco_sts; }
-static uint32_t reset_tco_status(void) +static u32 reset_tco_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t tco_sts = inl(pmbase + TCO_STS); - uint32_t tco_en = inl(pmbase + TCO1_CNT); + u16 pmbase = get_pmbase(); + u32 tco_sts = inl(pmbase + TCO_STS); + u32 tco_en = inl(pmbase + TCO1_CNT);
outl(tco_sts, pmbase + TCO_STS); return tco_sts & tco_en; }
-uint32_t clear_tco_status(void) +u32 clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
-void enable_gpe(uint32_t mask) +void enable_gpe(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); + u16 pmbase = get_pmbase(); + u32 gpe0_en = inl(pmbase + GPE0_EN); gpe0_en |= mask; outl(gpe0_en, pmbase + GPE0_EN); }
-void disable_gpe(uint32_t mask) +void disable_gpe(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); + u16 pmbase = get_pmbase(); + u32 gpe0_en = inl(pmbase + GPE0_EN); gpe0_en &= ~mask; outl(gpe0_en, pmbase + GPE0_EN); } @@ -248,15 +248,15 @@ void disable_all_gpe(void) }
-static uint32_t reset_gpe_status(void) +static u32 reset_gpe_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl(pmbase + GPE0_STS); + u16 pmbase = get_pmbase(); + u32 gpe_sts = inl(pmbase + GPE0_STS); outl(gpe_sts, pmbase + GPE0_STS); return gpe_sts; }
-static uint32_t print_gpe_sts(uint32_t gpe_sts) +static u32 print_gpe_sts(u32 gpe_sts) { static const char *gpe_sts_bits[] = { [1] = "HOTPLUG", @@ -298,22 +298,22 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts) return gpe_sts; }
-uint32_t clear_gpe_status(void) +u32 clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
-static uint32_t reset_alt_status(void) +static u32 reset_alt_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); + u16 pmbase = get_pmbase(); + u32 alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI); return alt_gpio_smi; }
-static uint32_t print_alt_sts(uint32_t alt_gpio_smi) +static u32 print_alt_sts(u32 alt_gpio_smi) { - uint32_t alt_gpio_sts; + u32 alt_gpio_sts; static const char *alt_gpio_smi_sts_bits[] = { [0] = "SUS_GPIO_0", [1] = "SUS_GPIO_1", @@ -345,15 +345,15 @@ static uint32_t print_alt_sts(uint32_t alt_gpio_smi) return alt_gpio_smi; }
-uint32_t clear_alt_status(void) +u32 clear_alt_status(void) { return print_alt_sts(reset_alt_status()); }
void clear_pmc_status(void) { - uint32_t prsts; - uint32_t gen_pmcon1; + u32 prsts; + u32 gen_pmcon1;
prsts = read32(PMC_BASE_ADDRESS + PRSTS); gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..ad11a7f 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -141,7 +141,7 @@ static inline void set_acpi_sleep_type(int val) static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - uint16_t pm1; + u16 pm1;
if (!ps) return; diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index e855218..2ba1b13 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -88,8 +88,8 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
c = next_cache(c); c->magic = RAMSTAGE_CACHE_MAGIC; - c->entry_point = (uint32_t)rsl->entry; - c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry); + c->entry_point = (u32)rsl->entry; + c->load_address = (u32)cbmem_entry_start(rsl->cbmem_entry); c->size = cbmem_entry_size(rsl->cbmem_entry);
printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n", diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c index 592d1fe..20f4c67 100644 --- a/src/soc/intel/baytrail/romstage/gfx.c +++ b/src/soc/intel/baytrail/romstage/gfx.c @@ -24,8 +24,8 @@
void gfx_init(void) { - uint32_t ggc; - uint8_t msac; + u32 ggc; + u8 msac; const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC);
/* The GFX device needs to set the aperture, gtt stolen size, and diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index c58a42c..712e4d0 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -32,7 +32,7 @@
void tco_disable(void) { - uint32_t reg; + u32 reg;
reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); reg |= TCO_TMR_HALT; @@ -42,8 +42,8 @@ void tco_disable(void) /* This sequence signals the PUNIT to start running. */ void punit_init(void) { - uint32_t reg; - uint8_t rid; + u32 reg; + u8 rid; const struct device *dev; const struct soc_intel_baytrail_config *cfg = NULL;
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index a51853a..0341a3c 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -43,8 +43,8 @@ static void reset_system(void)
static void enable_smbus(void) { - uint32_t reg; - const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); + u32 reg; + const u32 smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
/* SMBus I/O BAR */ reg = SMBUS_BASE_ADDRESS | 2; @@ -71,12 +71,12 @@ static void ABI_X86 send_to_console(unsigned char b) static void print_dram_info(void) { const int mrc_ver_reg = 0xf0; - const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); - uint32_t reg; + const u32 soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); + u32 reg; int num_channels; int speed; - uint32_t ch0; - uint32_t ch1; + u32 ch0; + u32 ch1;
reg = pci_read_config32(soc_dev, mrc_ver_reg);
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index b69b532..866b326 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -44,12 +44,12 @@ #include <baytrail/smm.h> #include <baytrail/spi.h>
-static inline uint64_t timestamp_get(void) +static inline u64 timestamp_get(void) { return rdtscll(); }
-static inline tsc_t ts64_to_tsc(uint64_t ts) +static inline tsc_t ts64_to_tsc(u64 ts) { tsc_t tsc = { .lo = ts, @@ -70,8 +70,8 @@ static void *setup_stack_and_mttrs(void);
static void program_base_addresses(void) { - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + u32 reg; + const u32 lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
/* Memory Mapped IO registers. */ reg = PMC_BASE_ADDRESS | 2; @@ -100,7 +100,7 @@ static void spi_init(void) { const unsigned long scs = SPI_BASE_ADDRESS + SCS; const unsigned long bcr = SPI_BASE_ADDRESS + BCR; - uint32_t reg; + u32 reg;
/* Disable generating SMI when setting WPD bit. */ write32(scs, read32(scs) & ~SMIWPEN); @@ -113,7 +113,7 @@ static void spi_init(void) write32(bcr, reg); }
-static inline void mark_ts(struct romstage_params *rp, uint64_t ts) +static inline void mark_ts(struct romstage_params *rp, u64 ts) { struct romstage_timestamps *rt = &rp->ts;
@@ -123,7 +123,7 @@ static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
/* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) + u32 tsc_low, u32 tsc_hi) { struct romstage_params rp = { .bist = bist, @@ -131,7 +131,7 @@ void * asmlinkage romstage_main(unsigned long bist, };
/* Save initial timestamp from bootblock. */ - mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + mark_ts(&rp, (((u64)tsc_hi) << 32) | (u64)tsc_low); /* Save romstage begin */ mark_ts(&rp, timestamp_get());
@@ -289,7 +289,7 @@ void asmlinkage romstage_after_car(void) while (1); }
-static inline uint32_t *stack_push(u32 *stack, u32 value) +static inline u32 *stack_push(u32 *stack, u32 value) { stack = &stack[-1]; *stack = value; @@ -316,9 +316,9 @@ static void *setup_stack_and_mttrs(void) { unsigned long top_of_stack; int num_mtrrs; - uint32_t *slot; - uint32_t mtrr_mask_upper; - uint32_t top_of_ram; + u32 *slot; + u32 mtrr_mask_upper; + u32 top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */ top_of_stack = choose_top_of_stack() & ~3; @@ -357,7 +357,7 @@ static void *setup_stack_and_mttrs(void) slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++;
- top_of_ram = (uint32_t)cbmem_top(); + top_of_ram = (u32)cbmem_top(); /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the * start of the TSEG region. It is required to be 8MiB aligned. Set * this area as cacheable so it can be used later for ramstage before diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c index e46237a..2279f2e 100644 --- a/src/soc/intel/baytrail/romstage/uart.c +++ b/src/soc/intel/baytrail/romstage/uart.c @@ -26,7 +26,7 @@
void byt_config_com1_and_enable(void) { - uint32_t reg; + u32 reg;
/* Enable the UART hardware for COM1. */ reg = 1; diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..5e7da2f 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -72,7 +72,7 @@ static const struct reg_script scc_after_dll[] = {
void baytrail_init_scc(void) { - uint32_t dll_values; + u32 dll_values;
printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n");
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index a2718e2..4dd6636 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -99,9 +99,9 @@ static void busmaster_disable_on_bus(int bus)
static void southbridge_smi_sleep(void) { - uint32_t reg32; - uint8_t slp_typ; - uint16_t pmbase = get_pmbase(); + u32 reg32; + u8 slp_typ; + u16 pmbase = get_pmbase();
/* First, disable further SMIs */ disable_smi(SLP_SMI_EN); @@ -179,7 +179,7 @@ static void southbridge_smi_sleep(void) * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t100_smm_state_save_area_t *state; int node; @@ -214,7 +214,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) static void southbridge_smi_gsmi(void) { u32 *ret, *param; - uint8_t sub_command; + u8 sub_command; em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(ELOG_GSMI_APM_CNT);
@@ -223,7 +223,7 @@ static void southbridge_smi_gsmi(void)
/* Command and return value in EAX */ ret = (u32*)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); + sub_command = (u8)(*ret >> 8);
/* Parameter buffer in EBX */ param = (u32*)&io_smi->rbx; @@ -234,7 +234,7 @@ static void southbridge_smi_gsmi(void) #endif static void southbridge_smi_apmc(void) { - uint8_t reg8; + u8 reg8; em64t100_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */ @@ -272,7 +272,7 @@ static void southbridge_smi_apmc(void) state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); + gnvs = (global_nvs_t *)((u32)state->rbx); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } @@ -289,7 +289,7 @@ static void southbridge_smi_apmc(void)
static void southbridge_smi_pm1(void) { - uint16_t pm1_sts = clear_pm1_status(); + u16 pm1_sts = clear_pm1_status();
/* While OSPM is not active, poweroff immediately * on a power button event. @@ -311,7 +311,7 @@ static void southbridge_smi_gpe0(void)
static void southbridge_smi_tco(void) { - uint32_t tco_sts = clear_tco_status(); + u32 tco_sts = clear_tco_status();
/* Any TCO event? */ if (!tco_sts) @@ -325,7 +325,7 @@ static void southbridge_smi_tco(void)
static void southbridge_smi_periodic(void) { - uint32_t reg32; + u32 reg32;
reg32 = inl(get_pmbase() + SMI_EN);
@@ -376,7 +376,7 @@ static const smi_handler_t southbridge_smi[32] = { void southbridge_smi_handler(void) { int i; - uint32_t smi_sts; + u32 smi_sts;
/* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index daf759d..b3d7471 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -32,16 +32,16 @@ #include <baytrail/smm.h>
/* Save settings which will be committed in SMI functions. */ -static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; +static u32 smm_save_params[SMM_SAVE_PARAM_COUNT];
-void southcluster_smm_save_param(int param, uint32_t data) +void southcluster_smm_save_param(int param, u32 data) { smm_save_params[param] = data; }
void southcluster_smm_clear_state(void) { - uint32_t smi_en; + u32 smi_en;
/* Log events from chipset before clearing */ southcluster_log_state(); @@ -68,8 +68,8 @@ static void southcluster_smm_route_gpios(void) { const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT; const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; - uint32_t alt_gpio_reg = 0; - uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; + u32 alt_gpio_reg = 0; + u32 route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; int i;
printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg); @@ -91,7 +91,7 @@ static void southcluster_smm_route_gpios(void)
void southcluster_smm_enable_smi(void) { - uint16_t pm1_events = PWRBTN_EN | GBL_EN; + u16 pm1_events = PWRBTN_EN | GBL_EN;
printk(BIOS_DEBUG, "Enabling SMIs.\n"); if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE]) @@ -127,7 +127,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) "outb %%al, %%dx\n\t" : /* ignore result */ : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), + "b" ((u32)gnvs), "d" (APM_CNT) ); } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..7d1fb3a 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -127,7 +127,7 @@ static void sc_read_resources(device_t dev)
static void sc_rtc_init(void) { - uint32_t gen_pmcon1; + u32 gen_pmcon1; int rtc_fail; struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
@@ -156,7 +156,7 @@ static void sc_rtc_init(void) */ static void com1_configure_resume(device_t dev) { - const uint16_t port = 0x3f8; + const u16 port = 0x3f8;
/* Is the UART I/O port enabled? */ if (!(pci_read_config32(dev, UART_CONT) & 1)) @@ -228,8 +228,8 @@ static void sc_disable_devfn(device_t dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; - uint32_t mask = 0; - uint32_t mask2 = 0; + u32 mask = 0; + u32 mask2 = 0;
switch (dev->path.pci.devfn) { case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): @@ -335,7 +335,7 @@ static void sc_disable_devfn(device_t dev)
static inline void set_d3hot_bits(device_t dev, int offset) { - uint32_t reg8; + u32 reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); reg8 = pci_read_config8(dev, offset + 4); reg8 |= 0x3; @@ -480,7 +480,7 @@ static int place_device_in_d3hot(device_t dev) /* Common PCI device function disable. */ void southcluster_enable_dev(device_t dev) { - uint32_t reg32; + u32 reg32;
if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8605dfc..3e92eae 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -69,51 +69,51 @@ typedef struct spi_slave ich_spi_slave; static int ichspi_lock = 0;
typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; + u32 bfpr; + u16 hsfs; + u16 hsfc; + u32 faddr; + u32 _reserved0; + u32 fdata[16]; + u32 frap; + u32 freg[5]; + u32 _reserved1[3]; + u32 pr[5]; + u32 _reserved2[2]; + u8 ssfs; + u8 ssfc[3]; + u16 preop; + u16 optype; + u8 opmenu[8]; + u32 bbar; + u8 _reserved3[12]; + u32 fdoc; + u32 fdod; + u8 _reserved4[8]; + u32 afc; + u32 lvscc; + u32 uvscc; + u8 _reserved5[4]; + u32 fpb; + u8 _reserved6[28]; + u32 srdl; + u32 srdc; + u32 srd; } __attribute__((packed)) ich9_spi_regs;
typedef struct ich_spi_controller { int locked;
- uint8_t *opmenu; + u8 *opmenu; int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; + u16 *preop; + u16 *optype; + u32 *addr; + u8 *data; unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; + u8 *status; + u16 *control; + u32 *bbar; } ich_spi_controller;
static ich_spi_controller cntlr; @@ -217,22 +217,22 @@ static void writel_(u32 b, const void *addr)
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) +#define readb_(a) read8((u32)a) +#define readw_(a) read16((u32)a) +#define readl_(a) read32((u32)a) +#define writeb_(val, addr) write8((u32)addr, val) +#define writew_(val, addr) write16((u32)addr, val) +#define writel_(val, addr) write32((u32)addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
-static void write_reg(const void *value, void *dest, uint32_t size) +static void write_reg(const void *value, void *dest, u32 size) { - const uint8_t *bvalue = value; - uint8_t *bdest = dest; + const u8 *bvalue = value; + u8 *bdest = dest;
while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); + writel_(*(const u32 *)bvalue, bdest); bdest += 4; bvalue += 4; size -= 4; } while (size) { @@ -241,13 +241,13 @@ static void write_reg(const void *value, void *dest, uint32_t size) } }
-static void read_reg(const void *src, void *value, uint32_t size) +static void read_reg(const void *src, void *value, u32 size) { - const uint8_t *bsrc = src; - uint8_t *bvalue = value; + const u8 *bsrc = src; + u8 *bvalue = value;
while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); + *(u32 *)bvalue = readl_(bsrc); bsrc += 4; bvalue += 4; size -= 4; } while (size) { @@ -256,10 +256,10 @@ static void read_reg(const void *src, void *value, uint32_t size) } }
-static void ich_set_bbar(uint32_t minaddr) +static void ich_set_bbar(u32 minaddr) { - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; + const u32 bbar_mask = 0x00ffff00; + u32 ichspi_bbar;
minaddr &= bbar_mask; ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; @@ -286,7 +286,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { device_t dev; - uint32_t sbase; + u32 sbase;
#ifdef __SMM__ dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); @@ -308,10 +308,10 @@ void spi_init(void) cntlr.menubytes = sizeof(ich9_spi->opmenu); cntlr.optype = &ich9_spi->optype; cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.data = (u8 *)ich9_spi->fdata; cntlr.databytes = sizeof(ich9_spi->fdata); cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.control = (u16 *)ich9_spi->ssfc; cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; ich_set_bbar(0); @@ -340,13 +340,13 @@ void spi_release_bus(struct spi_slave *slave) }
typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; + const u8 *out; + u32 bytesout; + u8 *in; + u32 bytesin; + u8 type; + u8 opcode; + u32 offset; } spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes) @@ -397,8 +397,8 @@ static void spi_setup_type(spi_transaction *trans)
static int spi_setup_opcode(spi_transaction *trans) { - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + u16 optypes; + u8 opmenu[cntlr.menubytes];
trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -411,8 +411,8 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; } else { /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; + u8 optype; + u16 opcode_index;
/* Write Enable is handled as atomic prefix */ if (trans->opcode == SPI_OPCODE_WREN) @@ -457,9 +457,9 @@ static int spi_setup_offset(spi_transaction *trans) return 0; case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); + trans->offset = ((u32)trans->out[0] << 16) | + ((u32)trans->out[1] << 8) | + ((u32)trans->out[2] << 0); spi_use_out(trans, 3); return 1; default: @@ -503,8 +503,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { - uint16_t control; - int16_t opcode_index; + u16 control; + s16 opcode_index; int with_address; int status;
@@ -598,7 +598,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * been sent. */ while (trans.bytesout || trans.bytesin) { - uint32_t data_length; + u32 data_length;
/* SPI addresses are 24 bit only */ writel_(trans.offset & 0x00FFFFFF, cntlr.addr); diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 5e7b72b..e66ce7a 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -229,7 +229,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
void acpi_fill_in_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const u16 pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; @@ -583,7 +583,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); acpi_madt_irqoverride_t *irqovr; - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + u16 flags = MP_IRQ_TRIGGER_LEVEL;
/* INT_SRC_OVR */ irqovr = (void *)current; diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index b5f82b2..9b2b34d 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -23,7 +23,7 @@
static void bootblock_northbridge_init(void) { - uint32_t reg; + u32 reg;
/* * The "io" variant of the config access is explicitly used to diff --git a/src/soc/intel/broadwell/monotonic_timer.c b/src/soc/intel/broadwell/monotonic_timer.c index ace9e60..7c5cd79 100644 --- a/src/soc/intel/broadwell/monotonic_timer.c +++ b/src/soc/intel/broadwell/monotonic_timer.c @@ -25,10 +25,10 @@ static struct monotonic_counter { int initialized; struct mono_time time; - uint32_t last_value; + u32 last_value; } mono_counter;
-static inline uint32_t read_counter_msr(void) +static inline u32 read_counter_msr(void) { /* Even though the MSR is 64-bit it is assumed that the hardware * is polled frequently enough to only use the lower 32-bits. */ @@ -41,8 +41,8 @@ static inline uint32_t read_counter_msr(void)
void timer_monotonic_get(struct mono_time *mt) { - uint32_t current_tick; - uint32_t usecs_elapsed; + u32 current_tick; + u32 usecs_elapsed;
if (!mono_counter.initialized) { mono_counter.last_value = read_counter_msr(); diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 0563064..1d319b2 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -32,7 +32,7 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - uint16_t pm1; + u16 pm1;
if (!ps) return; diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..1f571a3 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -93,8 +93,8 @@ static void cache_refcode(const struct rmod_stage_load *rsl)
c = next_cache(c); c->magic = RAMSTAGE_CACHE_MAGIC; - c->entry_point = (uint32_t)rsl->entry; - c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry); + c->entry_point = (u32)rsl->entry; + c->load_address = (u32)cbmem_entry_start(rsl->cbmem_entry); c->size = cbmem_entry_size(rsl->cbmem_entry);
printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n", diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 4a5a47c..4545948 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -38,12 +38,12 @@ #include <broadwell/romstage.h> #include <broadwell/spi.h>
-static inline uint64_t timestamp_get(void) +static inline u64 timestamp_get(void) { return rdtscll(); }
-static inline tsc_t ts64_to_tsc(uint64_t ts) +static inline tsc_t ts64_to_tsc(u64 ts) { tsc_t tsc = { .lo = ts, @@ -52,7 +52,7 @@ static inline tsc_t ts64_to_tsc(uint64_t ts) return tsc; }
-static inline void mark_ts(struct romstage_params *rp, uint64_t ts) +static inline void mark_ts(struct romstage_params *rp, u64 ts) { struct romstage_timestamps *rt = &rp->ts;
@@ -62,7 +62,7 @@ static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
/* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) + u32 tsc_low, u32 tsc_hi) { struct romstage_params rp = { .bist = bist, @@ -72,7 +72,7 @@ void * asmlinkage romstage_main(unsigned long bist, post_code(0x30);
/* Save initial timestamp from bootblock. */ - mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + mark_ts(&rp, (((u64)tsc_hi) << 32) | (u64)tsc_low);
/* Save romstage begin */ mark_ts(&rp, timestamp_get()); diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c index 7f56629..11013e8 100644 --- a/src/soc/intel/broadwell/romstage/stack.c +++ b/src/soc/intel/broadwell/romstage/stack.c @@ -26,7 +26,7 @@ #include <cpu/x86/mtrr.h> #include <broadwell/romstage.h>
-static inline uint32_t *stack_push(u32 *stack, u32 value) +static inline u32 *stack_push(u32 *stack, u32 value) { stack = &stack[-1]; *stack = value; @@ -53,9 +53,9 @@ void *setup_stack_and_mttrs(void) { unsigned long top_of_stack; int num_mtrrs; - uint32_t *slot; - uint32_t mtrr_mask_upper; - uint32_t top_of_ram; + u32 *slot; + u32 mtrr_mask_upper; + u32 top_of_ram;
/* Top of stack needs to be aligned to a 4-byte boundary. */ top_of_stack = choose_top_of_stack() & ~3; @@ -94,7 +94,7 @@ void *setup_stack_and_mttrs(void) slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++;
- top_of_ram = (uint32_t)cbmem_top(); + top_of_ram = (u32)cbmem_top(); /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the * start of the TSEG region. It is required to be 8MiB aligned. Set * this area as cacheable so it can be used later for ramstage before diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index eeffda0..33e8a03 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -65,51 +65,51 @@ typedef struct spi_slave ich_spi_slave; static int ichspi_lock = 0;
typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; + u32 bfpr; + u16 hsfs; + u16 hsfc; + u32 faddr; + u32 _reserved0; + u32 fdata[16]; + u32 frap; + u32 freg[5]; + u32 _reserved1[3]; + u32 pr[5]; + u32 _reserved2[2]; + u8 ssfs; + u8 ssfc[3]; + u16 preop; + u16 optype; + u8 opmenu[8]; + u32 bbar; + u8 _reserved3[12]; + u32 fdoc; + u32 fdod; + u8 _reserved4[8]; + u32 afc; + u32 lvscc; + u32 uvscc; + u8 _reserved5[4]; + u32 fpb; + u8 _reserved6[28]; + u32 srdl; + u32 srdc; + u32 srd; } __attribute__((packed)) ich9_spi_regs;
typedef struct ich_spi_controller { int locked;
- uint8_t *opmenu; + u8 *opmenu; int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; + u16 *preop; + u16 *optype; + u32 *addr; + u8 *data; unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; + u8 *status; + u16 *control; + u32 *bbar; } ich_spi_controller;
static ich_spi_controller cntlr; @@ -213,22 +213,22 @@ static void writel_(u32 b, const void *addr)
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) +#define readb_(a) read8((u32)a) +#define readw_(a) read16((u32)a) +#define readl_(a) read32((u32)a) +#define writeb_(val, addr) write8((u32)addr, val) +#define writew_(val, addr) write16((u32)addr, val) +#define writel_(val, addr) write32((u32)addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
-static void write_reg(const void *value, void *dest, uint32_t size) +static void write_reg(const void *value, void *dest, u32 size) { - const uint8_t *bvalue = value; - uint8_t *bdest = dest; + const u8 *bvalue = value; + u8 *bdest = dest;
while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); + writel_(*(const u32 *)bvalue, bdest); bdest += 4; bvalue += 4; size -= 4; } while (size) { @@ -237,13 +237,13 @@ static void write_reg(const void *value, void *dest, uint32_t size) } }
-static void read_reg(const void *src, void *value, uint32_t size) +static void read_reg(const void *src, void *value, u32 size) { - const uint8_t *bsrc = src; - uint8_t *bvalue = value; + const u8 *bsrc = src; + u8 *bvalue = value;
while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); + *(u32 *)bvalue = readl_(bsrc); bsrc += 4; bvalue += 4; size -= 4; } while (size) { @@ -252,10 +252,10 @@ static void read_reg(const void *src, void *value, uint32_t size) } }
-static void ich_set_bbar(uint32_t minaddr) +static void ich_set_bbar(u32 minaddr) { - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; + const u32 bbar_mask = 0x00ffff00; + u32 ichspi_bbar;
minaddr &= bbar_mask; ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; @@ -281,25 +281,25 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
void spi_init(void) { - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ - uint8_t bios_cntl; + u8 *rcrb; /* Root Complex Register Block */ + u32 rcba; /* Root Complex Base Address */ + u8 bios_cntl; device_t dev = PCH_DEV_LPC; ich9_spi_regs *ich9_spi;
pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); + rcrb = (u8 *)(rcba & 0xffffc000); ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; cntlr.opmenu = ich9_spi->opmenu; cntlr.menubytes = sizeof(ich9_spi->opmenu); cntlr.optype = &ich9_spi->optype; cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.data = (u8 *)ich9_spi->fdata; cntlr.databytes = sizeof(ich9_spi->fdata); cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.control = (u16 *)ich9_spi->ssfc; cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; ich_set_bbar(0); @@ -331,13 +331,13 @@ void spi_release_bus(struct spi_slave *slave) }
typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; + const u8 *out; + u32 bytesout; + u8 *in; + u32 bytesin; + u8 type; + u8 opcode; + u32 offset; } spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes) @@ -388,8 +388,8 @@ static void spi_setup_type(spi_transaction *trans)
static int spi_setup_opcode(spi_transaction *trans) { - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + u16 optypes; + u8 opmenu[cntlr.menubytes];
trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -402,8 +402,8 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; } else { /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; + u8 optype; + u16 opcode_index;
/* Write Enable is handled as atomic prefix */ if (trans->opcode == SPI_OPCODE_WREN) @@ -448,9 +448,9 @@ static int spi_setup_offset(spi_transaction *trans) return 0; case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); + trans->offset = ((u32)trans->out[0] << 16) | + ((u32)trans->out[1] << 8) | + ((u32)trans->out[2] << 0); spi_use_out(trans, 3); return 1; default: @@ -494,8 +494,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { - uint16_t control; - int16_t opcode_index; + u16 control; + s16 opcode_index; int with_address; int status;
@@ -589,7 +589,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * been sent. */ while (trans.bytesout || trans.bytesin) { - uint32_t data_length; + u32 data_length;
/* SPI addresses are 24 bit only */ /* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/penti... */ diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 74c43f2..2d842b2 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -185,10 +185,10 @@ struct map_entry { };
static void read_map_entry(device_t dev, struct map_entry *entry, - uint64_t *result) + u64 *result) { - uint64_t value; - uint64_t mask; + u64 value; + u64 mask;
/* All registers are on a 1MiB granularity. */ mask = ((1ULL<<20)-1); @@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), };
-static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(device_t dev, u64 *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } }
-static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(device_t dev, u64 *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -278,7 +278,7 @@ static void mc_add_dram_resources(device_t dev) unsigned long touud_k; unsigned long index; struct resource *resource; - uint64_t mc_values[NUM_MAP_ENTRIES]; + u64 mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg;
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 8f0d18f..a7615e4 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -33,7 +33,7 @@ * mrc_saved_data objects.*/ struct mrc_data_region { void *base; - uint32_t size; + u32 size; };
/* common code */ @@ -82,7 +82,7 @@ static int mrc_cache_in_region(const struct mrc_data_region *region, static int mrc_cache_valid(const struct mrc_data_region *region, const struct mrc_saved_data *cache) { - uint32_t checksum; + u32 checksum;
if (cache->signature != MRC_DATA_SIGNATURE) return 0; @@ -209,7 +209,7 @@ static int mrc_slot_valid(const struct mrc_data_region *region, uintptr_t region_end; uintptr_t slot_end; uintptr_t slot_begin; - uint32_t size; + u32 size;
region_begin = (uintptr_t)region->base; region_end = region_begin + region->size; diff --git a/src/soc/intel/common/nvm.c b/src/soc/intel/common/nvm.c index 791422f..01e7cb6 100644 --- a/src/soc/intel/common/nvm.c +++ b/src/soc/intel/common/nvm.c @@ -47,15 +47,15 @@ static int nvm_init(void) }
/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) +static inline u32 to_flash_offset(void *p) { return CONFIG_ROM_SIZE + (uintptr_t)p; }
int nvm_is_erased(const void *start, size_t size) { - const uint8_t *cur = start; - const uint8_t erased_value = 0xff; + const u8 *cur = start; + const u8 erased_value = 0xff;
while (size > 0) { if (*cur != erased_value) diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb0dc87..9393a5c 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -558,7 +558,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci_irq = acpi_sci_irq(); acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + u16 sci_flags = MP_IRQ_TRIGGER_LEVEL;
/* INT_SRC_OVR */ irqovr = (void *)current; diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index e8f5572..6525e33 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -47,7 +47,7 @@ static void check_for_warm_reset(void) } }
-static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +static void set_var_mtrr(int reg, u32 base, u32 size, int type) { msr_t basem, maskm; basem.lo = base | type; @@ -63,7 +63,7 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) */ static void enable_spi_prefetch(void) { - uint32_t bcr = SPI_BASE_ADDRESS + BCR; + u32 bcr = SPI_BASE_ADDRESS + BCR; /* Enable caching and prefetching in the SPI controller. */ write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); } @@ -85,7 +85,7 @@ static void enable_rom_caching(void)
static void setup_mmconfig(void) { - uint32_t reg; + u32 reg;
/* Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to @@ -101,13 +101,13 @@ static void setup_mmconfig(void) pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); }
-static const uint8_t lpc_pads[12] = { +static const u8 lpc_pads[12] = { 70, 68, 67, 66, 69, 71, 65, 72, 86, 90, 88, 92, };
static void set_up_lpc_pads(void) { - uint32_t reg = IO_BASE_ADDRESS | SET_BAR_ENABLE; + u32 reg = IO_BASE_ADDRESS | SET_BAR_ENABLE; pci_write_config32(LPC_BDF, IOBASE, reg);
for (reg = 0; reg < 12; reg++) diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 1d8c6ea..125329d 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -133,9 +133,9 @@ static const struct cpu_driver driver __cpu_driver = { */
struct smm_relocation_attrs { - uint32_t smbase; - uint32_t smrr_base; - uint32_t smrr_mask; + u32 smbase; + u32 smrr_base; + u32 smrr_mask; };
static struct smm_relocation_attrs relo_attrs; @@ -236,11 +236,11 @@ static int install_permanent_handler(int num_cpus) static int smm_load_handlers(void) { /* All range registers are aligned to 4KiB */ - const uint32_t rmask = ~((1 << 12) - 1); + const u32 rmask = ~((1 << 12) - 1); const struct pattrs *pattrs = pattrs_get();
/* Initialize global tracking state. */ - relo_attrs.smbase = (uint32_t)smm_region_start(); + relo_attrs.smbase = (u32)smm_region_start(); relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; relo_attrs.smrr_mask |= MTRRphysMaskValid; diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..4af63cb 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -285,7 +285,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) { FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; - uint32_t prev_sleep_state; + u32 prev_sleep_state;
/* Get previous sleep state but don't clear */ prev_sleep_state = chipset_prev_sleep_state(0); diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index aeb0998..d7c9f76 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -185,7 +185,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios, static void setup_gpio_route(const struct soc_gpio_map *sus, const struct soc_gpio_map *core) { - uint32_t route_reg = 0; + u32 route_reg = 0; int i;
for (i = 0; i < 8; i++) { @@ -255,9 +255,9 @@ struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) * @param gpio_num The GPIO number being read * @return The current input or output value of the GPIO */ -uint8_t read_score_gpio(uint8_t gpio_num) +u8 read_score_gpio(u8 gpio_num) { - uint8_t retval = 0; + u8 retval = 0; if (gpio_num < GPSCORE_COUNT) retval = score_get_gpio(gpscore_gpio_to_pad[gpio_num]);
@@ -269,9 +269,9 @@ uint8_t read_score_gpio(uint8_t gpio_num) * @param gpio_num The GPIO number being read * @return The current input or output value of the GPIO */ -uint8_t read_ssus_gpio(uint8_t gpio_num) +u8 read_ssus_gpio(u8 gpio_num) { - uint8_t retval = 0; + u8 retval = 0; if (gpio_num < GPSSUS_COUNT) retval = ssus_get_gpio(gpssus_gpio_to_pad[gpio_num]);
@@ -291,11 +291,11 @@ uint8_t read_ssus_gpio(uint8_t gpio_num) * io state: PAD_VAL_INPUT / PAD_VAL_OUTPUT * pad value: PAD_VAL_HIGH / PAD_VAL_LOW */ -static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num, - uint32_t pconf0, uint32_t pad_val) +static void configure_ssus_score_gpio(u8 ssus_gpio, u8 gpio_num, + u32 pconf0, u32 pad_val) { - uint32_t reg; - uint32_t pad_addr; + u32 reg; + u32 pad_addr; if (ssus_gpio) pad_addr = ssus_pconf0(gpssus_gpio_to_pad[gpio_num]); else @@ -334,7 +334,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num, /** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO * */ -void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) +void configure_ssus_gpio(u8 gpio_num, u32 pconf0, u32 pad_val) { configure_ssus_score_gpio(1, gpio_num, pconf0, pad_val); } @@ -342,7 +342,7 @@ void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) /** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO * */ -void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) +void configure_score_gpio(u8 gpio_num, u32 pconf0, u32 pad_val) { configure_ssus_score_gpio(0, gpio_num, pconf0, pad_val); } diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c index f892b20..009762b 100644 --- a/src/soc/intel/fsp_baytrail/iosf.c +++ b/src/soc/intel/fsp_baytrail/iosf.c @@ -27,27 +27,27 @@ #endif #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12))
-static inline void write_iosf_reg(int reg, uint32_t value) +static inline void write_iosf_reg(int reg, u32 value) { write32(IOSF_PCI_BASE + reg, value); } -static inline uint32_t read_iosf_reg(int reg) +static inline u32 read_iosf_reg(int reg) { return read32(IOSF_PCI_BASE + reg); } #else -static inline void write_iosf_reg(int reg, uint32_t value) +static inline void write_iosf_reg(int reg, u32 value) { pci_write_config32(IOSF_PCI_DEV, reg, value); } -static inline uint32_t read_iosf_reg(int reg) +static inline u32 read_iosf_reg(int reg) { return pci_read_config32(IOSF_PCI_DEV, reg); } #endif
/* Common sequences for all the port accesses. */ -static uint32_t iosf_read_port(uint32_t cr, int reg) +static u32 iosf_read_port(u32 cr, int reg) { cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); @@ -55,7 +55,7 @@ static uint32_t iosf_read_port(uint32_t cr, int reg) return read_iosf_reg(MDR_REG); }
-static void iosf_write_port(uint32_t cr, int reg, uint32_t val) +static void iosf_write_port(u32 cr, int reg, u32 val) { cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); @@ -68,44 +68,44 @@ static void iosf_write_port(uint32_t cr, int reg, uint32_t val) #define IOSF_WRITE(port) \ IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port)
-uint32_t iosf_bunit_read(int reg) +u32 iosf_bunit_read(int reg) { return iosf_read_port(IOSF_READ(BUNIT), reg); }
-void iosf_bunit_write(int reg, uint32_t val) +void iosf_bunit_write(int reg, u32 val) { iosf_write_port(IOSF_WRITE(BUNIT), reg, val); }
-uint32_t iosf_dunit_read(int reg) +u32 iosf_dunit_read(int reg) { return iosf_read_port(IOSF_READ(SYSMEMC), reg); }
-uint32_t iosf_dunit_ch0_read(int reg) +u32 iosf_dunit_ch0_read(int reg) { return iosf_dunit_read(reg); }
-uint32_t iosf_dunit_ch1_read(int reg) +u32 iosf_dunit_ch1_read(int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | + u32 cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | IOSF_PORT(IOSF_PORT_DUNIT_CH1); return iosf_read_port(cr, reg); }
-void iosf_dunit_write(int reg, uint32_t val) +void iosf_dunit_write(int reg, u32 val) { iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); }
-uint32_t iosf_lpss_read(int reg) +u32 iosf_lpss_read(int reg) { return iosf_read_port(IOSF_READ(LPSS), reg); }
-void iosf_lpss_write(int reg, uint32_t val) +void iosf_lpss_write(int reg, u32 val) { return iosf_write_port(IOSF_WRITE(LPSS), reg, val); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..897ebc4 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -82,9 +82,9 @@ static const int legacy_hole_size_k = 384; /* * Get the top of low memory for use by ACPI */ -uint32_t nc_read_top_of_low_memory(void) +u32 nc_read_top_of_low_memory(void) { - uint32_t fsp_mem_base = 0; + u32 fsp_mem_base = 0; GetLowMemorySize(&fsp_mem_base);
return fsp_mem_base; @@ -145,8 +145,8 @@ static void mc_add_dram_resources(device_t dev) { u32 bmbound, bsmmrrl; int index = 0; - uint64_t highmem_size = 0; - uint32_t fsp_mem_base = 0; + u64 highmem_size = 0; + u32 fsp_mem_base = 0;
GetHighMemorySize(&highmem_size); GetLowMemorySize(&fsp_mem_base); diff --git a/src/soc/intel/fsp_baytrail/nvm.c b/src/soc/intel/fsp_baytrail/nvm.c index 0224463..3a51946 100644 --- a/src/soc/intel/fsp_baytrail/nvm.c +++ b/src/soc/intel/fsp_baytrail/nvm.c @@ -48,7 +48,7 @@ static int nvm_init(void) }
/* Convert memory mapped pointer to flash offset. */ -static inline uint32_t to_flash_offset(void *p) +static inline u32 to_flash_offset(void *p) { #ifndef CONFIG_ROM_SIZE #error CONFIG_ROM_SIZE must be set. @@ -58,8 +58,8 @@ static inline uint32_t to_flash_offset(void *p)
int nvm_is_erased(const void *start, size_t size) { - const uint8_t *cur = start; - const uint8_t erased_value = 0xff; + const u8 *cur = start; + const u8 erased_value = 0xff;
while (size > 0) { if (*cur != erased_value) diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index aee3726..b0f746c 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -48,12 +48,12 @@ static device_t get_pcu_dev(void) } #endif
-uint16_t get_pmbase(void) +u16 get_pmbase(void) { return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; }
-static void print_num_status_bits(int num_bits, uint32_t status, +static void print_num_status_bits(int num_bits, u32 status, const char *bit_names[]) { int i; @@ -71,12 +71,12 @@ static void print_num_status_bits(int num_bits, uint32_t status, } }
-static void print_status_bits(uint32_t status, const char *bit_names[]) +static void print_status_bits(u32 status, const char *bit_names[]) { print_num_status_bits(32, status, bit_names); }
-static uint32_t print_smi_status(uint32_t smi_sts) +static u32 print_smi_status(u32 smi_sts) { static const char *smi_sts_bits[] = { [2] = "BIOS", @@ -108,60 +108,60 @@ static uint32_t print_smi_status(uint32_t smi_sts) return smi_sts; }
-static uint32_t reset_smi_status(void) +static u32 reset_smi_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_sts = inl(pmbase + SMI_STS); + u16 pmbase = get_pmbase(); + u32 smi_sts = inl(pmbase + SMI_STS); outl(smi_sts, pmbase + SMI_STS); return smi_sts; }
-uint32_t clear_smi_status(void) +u32 clear_smi_status(void) { return print_smi_status(reset_smi_status()); }
-void enable_smi(uint32_t mask) +void enable_smi(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); + u16 pmbase = get_pmbase(); + u32 smi_en = inl(pmbase + SMI_EN); smi_en |= mask; outl(smi_en, pmbase + SMI_EN); }
-void disable_smi(uint32_t mask) +void disable_smi(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t smi_en = inl(pmbase + SMI_EN); + u16 pmbase = get_pmbase(); + u32 smi_en = inl(pmbase + SMI_EN); smi_en &= ~mask; outl(smi_en, pmbase + SMI_EN); }
-void enable_pm1_control(uint32_t mask) +void enable_pm1_control(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); + u16 pmbase = get_pmbase(); + u32 pm1_cnt = inl(pmbase + PM1_CNT); pm1_cnt |= mask; outl(pm1_cnt, pmbase + PM1_CNT); }
-void disable_pm1_control(uint32_t mask) +void disable_pm1_control(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t pm1_cnt = inl(pmbase + PM1_CNT); + u16 pmbase = get_pmbase(); + u32 pm1_cnt = inl(pmbase + PM1_CNT); pm1_cnt &= ~mask; outl(pm1_cnt, pmbase + PM1_CNT); }
-static uint16_t reset_pm1_status(void) +static u16 reset_pm1_status(void) { - uint16_t pmbase = get_pmbase(); - uint16_t pm1_sts = inw(pmbase + PM1_STS); + u16 pmbase = get_pmbase(); + u16 pm1_sts = inw(pmbase + PM1_STS); outw(pm1_sts, pmbase + PM1_STS); return pm1_sts; }
-static uint16_t print_pm1_status(uint16_t pm1_sts) +static u16 print_pm1_status(u16 pm1_sts) { static const char *pm1_sts_bits[] = { [0] = "TMROF", @@ -184,17 +184,17 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) return pm1_sts; }
-uint16_t clear_pm1_status(void) +u16 clear_pm1_status(void) { return print_pm1_status(reset_pm1_status()); }
-void enable_pm1(uint16_t events) +void enable_pm1(u16 events) { outw(events, get_pmbase() + PM1_EN); }
-static uint32_t print_tco_status(uint32_t tco_sts) +static u32 print_tco_status(u32 tco_sts) { static const char *tco_sts_bits[] = { [3] = "TIMEOUT", @@ -211,33 +211,33 @@ static uint32_t print_tco_status(uint32_t tco_sts) return tco_sts; }
-static uint32_t reset_tco_status(void) +static u32 reset_tco_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t tco_sts = inl(pmbase + TCO_STS); - uint32_t tco_en = inl(pmbase + TCO1_CNT); + u16 pmbase = get_pmbase(); + u32 tco_sts = inl(pmbase + TCO_STS); + u32 tco_en = inl(pmbase + TCO1_CNT);
outl(tco_sts, pmbase + TCO_STS); return tco_sts & tco_en; }
-uint32_t clear_tco_status(void) +u32 clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
-void enable_gpe(uint32_t mask) +void enable_gpe(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); + u16 pmbase = get_pmbase(); + u32 gpe0_en = inl(pmbase + GPE0_EN); gpe0_en |= mask; outl(gpe0_en, pmbase + GPE0_EN); }
-void disable_gpe(uint32_t mask) +void disable_gpe(u32 mask) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe0_en = inl(pmbase + GPE0_EN); + u16 pmbase = get_pmbase(); + u32 gpe0_en = inl(pmbase + GPE0_EN); gpe0_en &= ~mask; outl(gpe0_en, pmbase + GPE0_EN); } @@ -248,15 +248,15 @@ void disable_all_gpe(void) }
-static uint32_t reset_gpe_status(void) +static u32 reset_gpe_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t gpe_sts = inl(pmbase + GPE0_STS); + u16 pmbase = get_pmbase(); + u32 gpe_sts = inl(pmbase + GPE0_STS); outl(gpe_sts, pmbase + GPE0_STS); return gpe_sts; }
-static uint32_t print_gpe_sts(uint32_t gpe_sts) +static u32 print_gpe_sts(u32 gpe_sts) { static const char *gpe_sts_bits[] = { [1] = "HOTPLUG", @@ -298,22 +298,22 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts) return gpe_sts; }
-uint32_t clear_gpe_status(void) +u32 clear_gpe_status(void) { return print_gpe_sts(reset_gpe_status()); }
-static uint32_t reset_alt_status(void) +static u32 reset_alt_status(void) { - uint16_t pmbase = get_pmbase(); - uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); + u16 pmbase = get_pmbase(); + u32 alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI); return alt_gpio_smi; }
-static uint32_t print_alt_sts(uint32_t alt_gpio_smi) +static u32 print_alt_sts(u32 alt_gpio_smi) { - uint32_t alt_gpio_sts; + u32 alt_gpio_sts; static const char *alt_gpio_smi_sts_bits[] = { [0] = "SUS_GPIO_0", [1] = "SUS_GPIO_1", @@ -345,15 +345,15 @@ static uint32_t print_alt_sts(uint32_t alt_gpio_smi) return alt_gpio_smi; }
-uint32_t clear_alt_status(void) +u32 clear_alt_status(void) { return print_alt_sts(reset_alt_status()); }
void clear_pmc_status(void) { - uint32_t prsts; - uint32_t gen_pmcon1; + u32 prsts; + u32 gen_pmcon1;
prsts = read32(PMC_BASE_ADDRESS + PRSTS); gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); diff --git a/src/soc/intel/fsp_baytrail/romstage/pmc.c b/src/soc/intel/fsp_baytrail/romstage/pmc.c index c048e06..8dcfabe 100644 --- a/src/soc/intel/fsp_baytrail/romstage/pmc.c +++ b/src/soc/intel/fsp_baytrail/romstage/pmc.c @@ -32,7 +32,7 @@
void tco_disable(void) { - uint32_t reg; + u32 reg;
reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); reg |= TCO_TMR_HALT; diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 37e40ba..5f9f037 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -29,12 +29,12 @@ static void print_dram_info(void) { const int mrc_ver_reg = 0xf0; - const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); - uint32_t reg; + const u32 soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); + u32 reg; int num_channels; int speed; - uint32_t ch0; - uint32_t ch1; + u32 ch0; + u32 ch1;
reg = pci_read_config32(soc_dev, mrc_ver_reg);
@@ -79,7 +79,7 @@ void report_platform_info(void) "Bay Trail-M (Mobile)", }; msr_t platform_id = rdmsr(MSR_IA32_PLATFORM_ID); - uint8_t variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK; + u8 variant = (platform_id.hi >> VARIANT_ID_BYTE) & VARIANT_ID_MASK;
printk(BIOS_INFO, "Baytrail Chip Variant: %s\n", variant < 4 ? baytrail_variants[variant] : "Unknown"); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 2619c96..1130e81 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -46,13 +46,13 @@ #include <console/cbmem_console.h>
/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ -uint32_t chipset_prev_sleep_state(uint32_t clear) +u32 chipset_prev_sleep_state(u32 clear) { /* Default to S0. */ - uint32_t prev_sleep_state = 0; - uint32_t pm1_sts; - uint32_t pm1_cnt; - uint32_t gen_pmcon1; + u32 prev_sleep_state = 0; + u32 pm1_sts; + u32 pm1_cnt; + u32 gen_pmcon1;
/* Read Power State */ pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); @@ -92,7 +92,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
static void program_base_addresses(void) { - uint32_t reg; + u32 reg;
/* Memory Mapped IO registers. */ reg = PMC_BASE_ADDRESS | SET_BAR_ENABLE; @@ -119,9 +119,9 @@ static void program_base_addresses(void)
static void spi_init(void) { - const uint32_t scs = SPI_BASE_ADDRESS + SCS; - const uint32_t bcr = SPI_BASE_ADDRESS + BCR; - uint32_t reg; + const u32 scs = SPI_BASE_ADDRESS + SCS; + const u32 bcr = SPI_BASE_ADDRESS + BCR; + u32 reg;
/* Disable generating SMI when setting WPD bit. */ write32(scs, read32(scs) & ~SMIWPEN); @@ -136,8 +136,8 @@ static void spi_init(void)
static void baytrail_rtc_init(void) { - uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0; - uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1); + u32 pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0; + u32 gen_pmcon1 = read32(pbase + GEN_PMCON1); int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) { @@ -156,8 +156,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; - uint32_t fd_mask = 0; - uint32_t fd2_mask = 0; + u32 fd_mask = 0; + u32 fd2_mask = 0;
post_code(0x40);
@@ -217,7 +217,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { int cbmem_was_initted; void *cbmem_hob_ptr; - uint32_t prev_sleep_state; + u32 prev_sleep_state; struct romstage_handoff *handoff;
#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) diff --git a/src/soc/intel/fsp_baytrail/romstage/uart.c b/src/soc/intel/fsp_baytrail/romstage/uart.c index 971067f..e98be14 100644 --- a/src/soc/intel/fsp_baytrail/romstage/uart.c +++ b/src/soc/intel/fsp_baytrail/romstage/uart.c @@ -26,7 +26,7 @@
void byt_config_com1_and_enable(void) { - uint32_t reg; + u32 reg;
/* Enable the legacy UART hardware. */ reg = 1; diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index d78288c..8dfee08 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -99,9 +99,9 @@ static void busmaster_disable_on_bus(int bus)
static void southbridge_smi_sleep(void) { - uint32_t reg32; - uint8_t slp_typ; - uint16_t pmbase = get_pmbase(); + u32 reg32; + u8 slp_typ; + u16 pmbase = get_pmbase();
/* First, disable further SMIs */ disable_smi(SLP_SMI_EN); @@ -179,7 +179,7 @@ static void southbridge_smi_sleep(void) * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { #ifndef CONFIG_MAX_CPUS #error CONFIG_MAX_CPUS must be set. @@ -217,7 +217,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) static void southbridge_smi_gsmi(void) { u32 *ret, *param; - uint8_t sub_command; + u8 sub_command; em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(ELOG_GSMI_APM_CNT);
@@ -226,7 +226,7 @@ static void southbridge_smi_gsmi(void)
/* Command and return value in EAX */ ret = (u32*)&io_smi->rax; - sub_command = (uint8_t)(*ret >> 8); + sub_command = (u8)(*ret >> 8);
/* Parameter buffer in EBX */ param = (u32*)&io_smi->rbx; @@ -237,7 +237,7 @@ static void southbridge_smi_gsmi(void) #endif static void southbridge_smi_apmc(void) { - uint8_t reg8; + u8 reg8; em64t100_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */ @@ -275,7 +275,7 @@ static void southbridge_smi_apmc(void) state = smi_apmc_find_state_save(reg8); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); + gnvs = (global_nvs_t *)((u32)state->rbx); smm_initialized = 1; printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } @@ -292,7 +292,7 @@ static void southbridge_smi_apmc(void)
static void southbridge_smi_pm1(void) { - uint16_t pm1_sts = clear_pm1_status(); + u16 pm1_sts = clear_pm1_status();
/* While OSPM is not active, poweroff immediately * on a power button event. @@ -314,7 +314,7 @@ static void southbridge_smi_gpe0(void)
static void southbridge_smi_tco(void) { - uint32_t tco_sts = clear_tco_status(); + u32 tco_sts = clear_tco_status();
/* Any TCO event? */ if (!tco_sts) @@ -328,7 +328,7 @@ static void southbridge_smi_tco(void)
static void southbridge_smi_periodic(void) { - uint32_t reg32; + u32 reg32;
reg32 = inl(get_pmbase() + SMI_EN);
@@ -379,7 +379,7 @@ static const smi_handler_t southbridge_smi[32] = { void southbridge_smi_handler(void) { int i; - uint32_t smi_sts; + u32 smi_sts;
/* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index d4b3d58..41602f7 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -33,16 +33,16 @@
/* Save the gpio route register. The settings are committed from * southcluster_smm_enable_smi(). */ -static uint32_t gpio_route; +static u32 gpio_route;
-void southcluster_smm_save_gpio_route(uint32_t route) +void southcluster_smm_save_gpio_route(u32 route) { gpio_route = route; }
void southcluster_smm_clear_state(void) { - uint32_t smi_en; + u32 smi_en;
/* Log events from chipset before clearing */ southcluster_log_state(); @@ -69,8 +69,8 @@ static void southcluster_smm_route_gpios(void) { const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT; const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; - uint32_t alt_gpio_reg = 0; - uint32_t route_reg = gpio_route; + u32 alt_gpio_reg = 0; + u32 route_reg = gpio_route; int i;
printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg); @@ -126,7 +126,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) "outb %%al, %%dx\n\t" : /* ignore result */ : "a" (APM_CNT_GNVS_UPDATE), - "b" ((uint32_t)gnvs), + "b" ((u32)gnvs), "d" (APM_CNT) ); } diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index d87935b..386e1ab 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -173,13 +173,13 @@ static void write_pci_config_irqs(void) { device_t irq_dev; device_t targ_dev; - uint8_t int_line = 0; - uint8_t original_int_pin = 0; - uint8_t new_int_pin = 0; - uint16_t current_bdf = 0; - uint16_t parent_bdf = 0; - uint8_t pirq = 0; - uint8_t device_num = 0; + u8 int_line = 0; + u8 original_int_pin = 0; + u8 new_int_pin = 0; + u16 current_bdf = 0; + u16 parent_bdf = 0; + u8 pirq = 0; + u8 device_num = 0; const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
if (ir == NULL) { @@ -413,8 +413,8 @@ static void sc_disable_devfn(device_t dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; - uint32_t fd_mask = 0; - uint32_t fd2_mask = 0; + u32 fd_mask = 0; + u32 fd2_mask = 0;
#define SET_DIS_MASK(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ @@ -459,7 +459,7 @@ static void sc_disable_devfn(device_t dev)
static inline void set_d3hot_bits(device_t dev, int offset) { - uint32_t reg8; + u32 reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); reg8 = pci_read_config8(dev, offset + 4); reg8 |= 0x3; @@ -565,7 +565,7 @@ static int place_device_in_d3hot(device_t dev) /* Common PCI device function disable. */ void southcluster_enable_dev(device_t dev) { - uint32_t reg32; + u32 reg32;
if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 0c3c63d..26e617c 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -66,51 +66,51 @@ typedef struct spi_slave ich_spi_slave; static int ichspi_lock = 0;
typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; + u32 bfpr; + u16 hsfs; + u16 hsfc; + u32 faddr; + u32 _reserved0; + u32 fdata[16]; + u32 frap; + u32 freg[5]; + u32 _reserved1[3]; + u32 pr[5]; + u32 _reserved2[2]; + u8 ssfs; + u8 ssfc[3]; + u16 preop; + u16 optype; + u8 opmenu[8]; + u32 bbar; + u8 _reserved3[12]; + u32 fdoc; + u32 fdod; + u8 _reserved4[8]; + u32 afc; + u32 lvscc; + u32 uvscc; + u8 _reserved5[4]; + u32 fpb; + u8 _reserved6[28]; + u32 srdl; + u32 srdc; + u32 srd; } __attribute__((packed)) ich9_spi_regs;
typedef struct ich_spi_controller { int locked;
- uint8_t *opmenu; + u8 *opmenu; int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; + u16 *preop; + u16 *optype; + u32 *addr; + u8 *data; unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; + u8 *status; + u16 *control; + u32 *bbar; } ich_spi_controller;
static ich_spi_controller cntlr; @@ -214,22 +214,22 @@ static void writel_(u32 b, const void *addr)
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) +#define readb_(a) read8((u32)a) +#define readw_(a) read16((u32)a) +#define readl_(a) read32((u32)a) +#define writeb_(val, addr) write8((u32)addr, val) +#define writew_(val, addr) write16((u32)addr, val) +#define writel_(val, addr) write32((u32)addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
-static void write_reg(const void *value, void *dest, uint32_t size) +static void write_reg(const void *value, void *dest, u32 size) { - const uint8_t *bvalue = value; - uint8_t *bdest = dest; + const u8 *bvalue = value; + u8 *bdest = dest;
while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); + writel_(*(const u32 *)bvalue, bdest); bdest += 4; bvalue += 4; size -= 4; } while (size) { @@ -238,13 +238,13 @@ static void write_reg(const void *value, void *dest, uint32_t size) } }
-static void read_reg(const void *src, void *value, uint32_t size) +static void read_reg(const void *src, void *value, u32 size) { - const uint8_t *bsrc = src; - uint8_t *bvalue = value; + const u8 *bsrc = src; + u8 *bvalue = value;
while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); + *(u32 *)bvalue = readl_(bsrc); bsrc += 4; bvalue += 4; size -= 4; } while (size) { @@ -253,10 +253,10 @@ static void read_reg(const void *src, void *value, uint32_t size) } }
-static void ich_set_bbar(uint32_t minaddr) +static void ich_set_bbar(u32 minaddr) { - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; + const u32 bbar_mask = 0x00ffff00; + u32 ichspi_bbar;
minaddr &= bbar_mask; ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; @@ -283,7 +283,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { device_t dev; - uint32_t sbase; + u32 sbase;
#ifdef __SMM__ dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); @@ -305,10 +305,10 @@ void spi_init(void) cntlr.menubytes = sizeof(ich9_spi->opmenu); cntlr.optype = &ich9_spi->optype; cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.data = (u8 *)ich9_spi->fdata; cntlr.databytes = sizeof(ich9_spi->fdata); cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.control = (u16 *)ich9_spi->ssfc; cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; ich_set_bbar(0); @@ -326,13 +326,13 @@ void spi_release_bus(struct spi_slave *slave) }
typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; + const u8 *out; + u32 bytesout; + u8 *in; + u32 bytesin; + u8 type; + u8 opcode; + u32 offset; } spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes) @@ -383,8 +383,8 @@ static void spi_setup_type(spi_transaction *trans)
static int spi_setup_opcode(spi_transaction *trans) { - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + u16 optypes; + u8 opmenu[cntlr.menubytes];
trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -397,8 +397,8 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; } else { /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; + u8 optype; + u16 opcode_index;
/* Write Enable is handled as atomic prefix */ if (trans->opcode == SPI_OPCODE_WREN) @@ -443,9 +443,9 @@ static int spi_setup_offset(spi_transaction *trans) return 0; case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); + trans->offset = ((u32)trans->out[0] << 16) | + ((u32)trans->out[1] << 8) | + ((u32)trans->out[2] << 0); spi_use_out(trans, 3); return 1; default: @@ -489,8 +489,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { - uint16_t control; - int16_t opcode_index; + u16 control; + s16 opcode_index; int with_address; int status;
@@ -583,7 +583,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * been sent. */ while (trans.bytesout || trans.bytesin) { - uint32_t data_length; + u32 data_length;
/* SPI addresses are 24 bit only */ writel_(trans.offset & 0x00FFFFFF, cntlr.addr); diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index 26c2559..9f410ef 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -30,7 +30,7 @@ static void do_bus_clear(int bus) { struct tegra_i2c_bus_info *info = &tegra_i2c_info[bus]; struct tegra_i2c_regs * const regs = info->base; - uint32_t bc; + u32 bc; int i, timeout_ms = 10;
// BUS CLEAR regs (from TRM): @@ -60,14 +60,14 @@ static void do_bus_clear(int bus) }
static int tegra_i2c_send_recv(int bus, int read, - uint32_t *headers, int header_words, - uint8_t *data, int data_len) + u32 *headers, int header_words, + u8 *data, int data_len) { struct tegra_i2c_bus_info *info = &tegra_i2c_info[bus]; struct tegra_i2c_regs * const regs = info->base;
while (data_len) { - uint32_t status = read32(®s->fifo_status); + u32 status = read32(®s->fifo_status); int tx_empty = status & I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK; tx_empty >>= I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT; int rx_full = status & I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK; @@ -82,7 +82,7 @@ static int tegra_i2c_send_recv(int bus, int read, if (!header_words) { if (read) { while (data_len && rx_full) { - uint32_t word = read32(®s->rx_fifo); + u32 word = read32(®s->rx_fifo); int todo = MIN(data_len, sizeof(word));
memcpy(data, &word, todo); @@ -92,7 +92,7 @@ static int tegra_i2c_send_recv(int bus, int read, } } else { while (data_len && tx_empty) { - uint32_t word; + u32 word; int todo = MIN(data_len, sizeof(word));
memcpy(&word, data, todo); @@ -104,7 +104,7 @@ static int tegra_i2c_send_recv(int bus, int read, } }
- uint32_t transfer_status = + u32 transfer_status = read32(®s->packet_transfer_status);
if (transfer_status & I2C_PKT_STATUS_NOACK_ADDR) { @@ -139,7 +139,7 @@ static int tegra_i2c_send_recv(int bus, int read, static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart, int read, void *data, int data_len) { - uint32_t headers[3]; + u32 headers[3];
if (restart && cont) { printk(BIOS_ERR, "%s: Repeat start and continue xfer are " @@ -154,7 +154,7 @@ static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart,
headers[1] = (data_len - 1) << IOHEADER_PAYLOADSIZE_SHIFT;
- uint32_t slave_addr = (chip << 1) | (read ? 1 : 0); + u32 slave_addr = (chip << 1) | (read ? 1 : 0); headers[2] = IOHEADER_I2C_REQ_ADDR_MODE_7BIT | (slave_addr << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT); if (read) @@ -171,7 +171,7 @@ static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart, static int i2c_transfer_segment(unsigned bus, unsigned chip, int restart, int read, void *buf, int len) { - const uint32_t max_payload = + const u32 max_payload = (IOHEADER_PAYLOADSIZE_MASK + 1) >> IOHEADER_PAYLOADSIZE_SHIFT;
while (len) { diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c index 858cb44..6d08799 100644 --- a/src/soc/nvidia/tegra/pingroup.c +++ b/src/soc/nvidia/tegra/pingroup.c @@ -22,14 +22,14 @@
#include "pingroup.h"
-static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE; +static u32 *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE;
-void pingroup_set_config(int group_index, uint32_t config) +void pingroup_set_config(int group_index, u32 config) { write32(config, &pingroup_regs[group_index]); }
-uint32_t pingroup_get_config(int group_index) +u32 pingroup_get_config(int group_index) { return read32(&pingroup_regs[group_index]); } diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c index 6e4b3ff..20ab630 100644 --- a/src/soc/nvidia/tegra/pinmux.c +++ b/src/soc/nvidia/tegra/pinmux.c @@ -22,14 +22,14 @@
#include "pinmux.h"
-static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE; +static u32 *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE;
-void pinmux_set_config(int pin_index, uint32_t config) +void pinmux_set_config(int pin_index, u32 config) { write32(config, &pinmux_regs[pin_index]); }
-uint32_t pinmux_get_config(int pin_index) +u32 pinmux_get_config(int pin_index) { return read32(&pinmux_regs[pin_index]); } diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index c5b06f4..b060e09 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -179,14 +179,14 @@ int clock_get_pll_input_khz(void)
void clock_init_arm_generic_timer(void) { - uint32_t freq = clock_get_osc_khz() * 1000; + u32 freq = clock_get_osc_khz() * 1000; // Set the cntfrq register. __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq));
// Record the system timer frequency. write32(freq, &sysctr->cntfid0); // Enable the system counter. - uint32_t cntcr = read32(&sysctr->cntcr); + u32 cntcr = read32(&sysctr->cntcr); cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; write32(cntcr, &sysctr->cntcr); } @@ -475,7 +475,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
void clock_cpu0_config_and_reset(void *entry) { - void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; + void * const evp_cpu_reset = (u8 *)TEGRA_EVP_BASE + 0x100;
write32(CONFIG_STACK_TOP, &maincpu_stack_pointer); write32((uintptr_t)entry, &maincpu_entry_point); @@ -495,7 +495,7 @@ void clock_cpu0_config_and_reset(void *entry) &clk_rst->super_cclk_div);
// Enable the clocks for CPUs 0-3. - uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); + u32 cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 9ad76f0..4606804 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -207,7 +207,7 @@ static int tegra_dc_init(struct display_controller *disp_ctrl) return 0; }
-uint32_t fb_base_mb(void) +u32 fb_base_mb(void) { return sdram_max_addressable_mb() - FB_SIZE_MB; } diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 0b519d6..fdbd6b3 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -32,7 +32,7 @@ enum {
/* UP tag registers. */ -static uint32_t *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); +static u32 *up_tag_ptr = (void *)(UP_TAG_BASE + 0x0); enum { UP_TAG_AVP = 0xaaaaaaaa }; @@ -40,27 +40,27 @@ enum {
/* Timer registers. */ -static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); +static u32 *timer_us_ptr = (void *)(TIMER_BASE + 0x10);
/* Clock and reset controller registers. */ -static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); +static u32 *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); enum { SWR_TRIG_SYS_RST = 0x1 << 2 };
-static uint32_t *clk_rst_cclk_burst_policy_ptr = (void *)(CLK_RST_BASE + 0x20); +static u32 *clk_rst_cclk_burst_policy_ptr = (void *)(CLK_RST_BASE + 0x20); enum { CCLK_PLLP_BURST_POLICY = 0x20004444 };
-static uint32_t *clk_rst_super_cclk_div_ptr = (void *)(CLK_RST_BASE + 0x24); +static u32 *clk_rst_super_cclk_div_ptr = (void *)(CLK_RST_BASE + 0x24); enum { SUPER_CDIV_ENB = 0x1 << 31 };
-static uint32_t *clk_rst_osc_ctrl_ptr = (void *)(CLK_RST_BASE + 0x50); +static u32 *clk_rst_osc_ctrl_ptr = (void *)(CLK_RST_BASE + 0x50); enum { OSC_XOE = 0x1 << 0, OSC_XOFS_SHIFT = 4, @@ -78,7 +78,7 @@ enum { OSC_FREQ_26 = 12 };
-static uint32_t *clk_rst_pllu_base_ptr = (void *)(CLK_RST_BASE + 0xc0); +static u32 *clk_rst_pllu_base_ptr = (void *)(CLK_RST_BASE + 0xc0); enum { PLLU_DIVM_SHIFT = 0, PLLU_DIVN_SHIFT = 8, @@ -87,42 +87,42 @@ enum { PLLU_BYPASS = 0x1 << 31 };
-static uint32_t *clk_rst_pllu_misc_ptr = (void *)(CLK_RST_BASE + 0xcc); +static u32 *clk_rst_pllu_misc_ptr = (void *)(CLK_RST_BASE + 0xcc); enum { PLLU_LFCON_SHIFT = 4, PLLU_CPCON_SHIFT = 8, PLLU_LOCK_ENABLE = 22 };
-static uint32_t *clk_rst_pllx_base_ptr = (void *)(CLK_RST_BASE + 0xe0); +static u32 *clk_rst_pllx_base_ptr = (void *)(CLK_RST_BASE + 0xe0); enum { PLLX_ENABLE = 0x1 << 30 };
-static uint32_t *clk_rst_rst_dev_u_clr_ptr = (void *)(CLK_RST_BASE + 0x314); +static u32 *clk_rst_rst_dev_u_clr_ptr = (void *)(CLK_RST_BASE + 0x314); enum { SWR_CSITE_RST = 0x1 << 9 };
-static uint32_t *clk_rst_clk_enb_l_set_ptr = (void *)(CLK_RST_BASE + 0x320); +static u32 *clk_rst_clk_enb_l_set_ptr = (void *)(CLK_RST_BASE + 0x320); enum { CLK_ENB_CPU = 0x1 << 0 };
-static uint32_t *clk_rst_clk_out_enb_u_set_ptr = +static u32 *clk_rst_clk_out_enb_u_set_ptr = (void *)(CLK_RST_BASE + 0x330); enum { CLK_ENB_CSITE = 0x1 << 9 };
-static uint32_t *clk_rst_cpu_softrst_ctrl2_ptr = +static u32 *clk_rst_cpu_softrst_ctrl2_ptr = (void *)(CLK_RST_BASE + 0x388); enum { CAR2PMC_CPU_ACK_WIDTH_SHIFT = 0, CAR2PMC_CPU_ACK_WIDTH_MASK = 0xfff << CAR2PMC_CPU_ACK_WIDTH_SHIFT };
-static uint32_t *clk_rst_clk_src_mselect_ptr = +static u32 *clk_rst_clk_src_mselect_ptr = (void *)(CLK_RST_BASE + 0x3b4); enum { MSELECT_CLK_DIV_SHIFT = 0, @@ -133,21 +133,21 @@ enum { MSELECT_CLK_SRC_PLLC3_OUT0 = 0x3 << MSELECT_CLK_SRC_SHIFT };
-static uint32_t *clk_rst_rst_dev_v_clr_ptr = (void *)(CLK_RST_BASE + 0x434); +static u32 *clk_rst_rst_dev_v_clr_ptr = (void *)(CLK_RST_BASE + 0x434); enum { SWR_MSELECT_RST = 0x1 << 3 };
-static uint32_t *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440); +static u32 *clk_rst_clk_enb_v_set_ptr = (void *)(CLK_RST_BASE + 0x440); enum { CLK_ENB_CPUG = 0x1 << 0, CLK_ENB_CPULP = 0x1 << 1, CLK_ENB_MSELECT = 0x1 << 3 };
-static uint32_t *clk_rst_rst_cpulp_cmplx_clr_ptr = +static u32 *clk_rst_rst_cpulp_cmplx_clr_ptr = (void *)(CLK_RST_BASE + 0x45c); -static uint32_t *clk_rst_rst_cpug_cmplx_clr_ptr = +static u32 *clk_rst_rst_cpug_cmplx_clr_ptr = (void *)(CLK_RST_BASE + 0x454); enum { CLR_CPURESET0 = 0x1 << 0, @@ -173,12 +173,12 @@ enum {
/* Reset vector. */
-static uint32_t *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100); +static u32 *evp_cpu_reset_ptr = (void *)(TEGRA_EVP_BASE + 0x100);
/* Flow controller registers. */ -static uint32_t *flow_ctlr_halt_cop_events_ptr = +static u32 *flow_ctlr_halt_cop_events_ptr = (void *)(FLOW_CTLR_BASE + 0x4); enum { EVENT_MSEC = 0x1 << 24, @@ -187,7 +187,7 @@ enum { FLOW_MODE_STOP = 2 << FLOW_MODE_SHIFT, };
-static uint32_t *flow_ctlr_cluster_control_ptr = +static u32 *flow_ctlr_cluster_control_ptr = (void *)(FLOW_CTLR_BASE + 0x2c); enum { FLOW_CLUSTER_ACTIVE_LP = 0x1 << 0 @@ -204,26 +204,26 @@ enum { PARTID_C1NC = 16 };
-static uint32_t *pmc_ctlr_clamp_status_ptr = (void *)(PMC_CTLR_BASE + 0x2c); +static u32 *pmc_ctlr_clamp_status_ptr = (void *)(PMC_CTLR_BASE + 0x2c);
-static uint32_t *pmc_ctlr_pwrgate_toggle_ptr = (void *)(PMC_CTLR_BASE + 0x30); +static u32 *pmc_ctlr_pwrgate_toggle_ptr = (void *)(PMC_CTLR_BASE + 0x30); enum { PWRGATE_TOGGLE_START = 0x1 << 8 };
-static uint32_t *pmc_ctlr_pwrgate_status_ptr = (void *)(PMC_CTLR_BASE + 0x38); +static u32 *pmc_ctlr_pwrgate_status_ptr = (void *)(PMC_CTLR_BASE + 0x38);
-static uint32_t *pmc_ctlr_scratch4_ptr = (void *)(PMC_CTLR_BASE + 0x60); +static u32 *pmc_ctlr_scratch4_ptr = (void *)(PMC_CTLR_BASE + 0x60); enum { PMC_SCRATCH4_LP = 0x1 << 31 };
-static uint32_t *pmc_ctlr_cpupwrgood_timer_ptr = +static u32 *pmc_ctlr_cpupwrgood_timer_ptr = (void *)(PMC_CTLR_BASE + 0xc8);
-static uint32_t *pmc_ctlr_scratch41_ptr = (void *)(PMC_CTLR_BASE + 0x140); +static u32 *pmc_ctlr_scratch41_ptr = (void *)(PMC_CTLR_BASE + 0x140);
-static uint32_t *pmc_ctlr_osc_edpd_over_ptr = (void *)(PMC_CTLR_BASE + 0x1a4); +static u32 *pmc_ctlr_osc_edpd_over_ptr = (void *)(PMC_CTLR_BASE + 0x1a4); enum { PMC_XOFS_SHIFT = 1, PMC_XOFS_MASK = 0x3f << PMC_XOFS_SHIFT @@ -232,9 +232,9 @@ enum {
/* Memory controller registers. */ -static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c); +static u32 *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c);
-static uint32_t *mc_video_protect_reg_ctrl_ptr = +static u32 *mc_video_protect_reg_ctrl_ptr = (void *)(MC_CTLR_BASE + 0x650); enum { VIDEO_PROTECT_WRITE_ACCESS_DISABLE = 0x1 << 0, @@ -244,13 +244,13 @@ enum {
/* System counter registers. */ -static uint32_t *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0); +static u32 *sysctr_cntcr_ptr = (void *)(SYSCTR_CTLR_BASE + 0x0); enum { TSC_CNTCR_ENABLE = 0x1 << 0, TSC_CNTCR_HDBG = 0x1 << 1 };
-static uint32_t *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20); +static u32 *sysctr_cntfid0_ptr = (void *)(SYSCTR_CTLR_BASE + 0x20);
@@ -262,22 +262,22 @@ static inline void __attribute__((always_inline)) for (;;); }
-inline static uint32_t read32(const void *addr) +inline static u32 read32(const void *addr) { - return *(volatile uint32_t *)addr; + return *(volatile u32 *)addr; }
-inline static void write32(uint32_t val, void *addr) +inline static void write32(u32 val, void *addr) { - *(volatile uint32_t *)addr = val; + *(volatile u32 *)addr = val; }
-inline static void setbits32(uint32_t bits, void *addr) +inline static void setbits32(u32 bits, void *addr) { write32(read32(addr) | bits, addr); }
-inline static void clrbits32(uint32_t bits, void *addr) +inline static void clrbits32(u32 bits, void *addr) { write32(read32(addr) & ~bits, addr); } @@ -290,7 +290,7 @@ static void __attribute__((noreturn)) reset(void)
static void udelay(unsigned usecs) { - uint32_t start = read32(timer_us_ptr); + u32 start = read32(timer_us_ptr); while (read32(timer_us_ptr) - start < usecs) ; } @@ -304,7 +304,7 @@ static int wakeup_on_lp(void) return !!(read32(pmc_ctlr_scratch4_ptr) & PMC_SCRATCH4_LP); }
-static uint32_t get_wakeup_vector(void) +static u32 get_wakeup_vector(void) { return read32(pmc_ctlr_scratch41_ptr); } @@ -322,10 +322,10 @@ static void config_oscillator(void) { // Read oscillator drive strength from OSC_EDPD_OVER.XOFS and copy // to OSC_CTRL.XOFS and set XOE. - uint32_t xofs = (read32(pmc_ctlr_osc_edpd_over_ptr) & + u32 xofs = (read32(pmc_ctlr_osc_edpd_over_ptr) & PMC_XOFS_MASK) >> PMC_XOFS_SHIFT;
- uint32_t osc_ctrl = read32(clk_rst_osc_ctrl_ptr); + u32 osc_ctrl = read32(clk_rst_osc_ctrl_ptr); osc_ctrl &= ~OSC_XOFS_MASK; osc_ctrl |= (xofs << OSC_XOFS_SHIFT); osc_ctrl |= OSC_XOE; @@ -335,7 +335,7 @@ static void config_oscillator(void) static void config_pllu(void) { // Figure out what parameters to use for PLLU. - uint32_t divm, divn, cpcon, lfcon; + u32 divm, divn, cpcon, lfcon; switch (get_osc_freq()) { case OSC_FREQ_12: case OSC_FREQ_48: @@ -372,10 +372,10 @@ static void config_pllu(void) }
// Configure PLLU. - uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE | + u32 base = PLLU_BYPASS | PLLU_OVERRIDE | (divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT); write32(base, clk_rst_pllu_base_ptr); - uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) | + u32 misc = (cpcon << PLLU_CPCON_SHIFT) | (lfcon << PLLU_LFCON_SHIFT); write32(misc, clk_rst_pllu_misc_ptr);
@@ -480,7 +480,7 @@ static void clear_cpu_resets(void)
static void power_on_partition(unsigned id) { - uint32_t bit = 0x1 << id; + u32 bit = 0x1 << id; if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) { // Partition is not on. Turn it on. write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr); @@ -511,7 +511,7 @@ static void power_on_main_cpu(void) * Save the original PMC_CPUPWRGOOD_TIMER register which we need to * restore after the CPU is powered up. */ - uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr); + u32 orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
write32(orig_timer * (408000000 / 32768), pmc_ctlr_cpupwrgood_timer_ptr); @@ -570,7 +570,7 @@ void lp0_resume(void) clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr);
// Set CAR2PMC_CPU_ACK_WIDTH to 408. - uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); + u32 ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr); ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK; ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT; write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr); @@ -600,21 +600,21 @@ void lp0_resume(void)
/* Header. */
-extern uint8_t blob_data; -extern uint8_t blob_data_size; -extern uint8_t blob_total_size; +extern u8 blob_data; +extern u8 blob_data_size; +extern u8 blob_total_size;
struct lp0_header { - uint32_t length_insecure; // Insecure total length. - uint32_t reserved[3]; - uint8_t rsa_modulus[256]; // RSA key modulus. - uint8_t aes_signature[16]; // AES signature. - uint8_t rsa_signature[256]; // RSA-PSS signature. - uint8_t random_aes_block[16]; // Random data, may be zero. - uint32_t length_secure; // Secure total length. - uint32_t destination; // Where to load the blob in iRAM. - uint32_t entry_point; // Entry point for the blob. - uint32_t code_length; // Length of just the data. + u32 length_insecure; // Insecure total length. + u32 reserved[3]; + u8 rsa_modulus[256]; // RSA key modulus. + u8 aes_signature[16]; // AES signature. + u8 rsa_signature[256]; // RSA-PSS signature. + u8 random_aes_block[16]; // Random data, may be zero. + u32 length_secure; // Secure total length. + u32 destination; // Where to load the blob in iRAM. + u32 entry_point; // Entry point for the blob. + u32 code_length; // Length of just the data. } __attribute__((packed));
struct lp0_header header __attribute__((section(".header"))) = diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 760d058..0a9a5e9 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -32,12 +32,12 @@ static int partition_powered(int id) return read32(&pmc->pwrgate_status) & (0x1 << id); }
-static void power_ungate_partition(uint32_t id) +static void power_ungate_partition(u32 id) { printk(BIOS_INFO, "Ungating power partition %d.\n", id);
if (!partition_powered(id)) { - uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle); + u32 pwrgate_toggle = read32(&pmc->pwrgate_toggle); pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; @@ -59,7 +59,7 @@ static void power_ungate_partition(uint32_t id) void power_enable_cpu_rail(void) { // Set the power gate timer multiplier to 8 (why 8?). - uint32_t pwrgate_timer_mult = read32(&pmc->pwrgate_timer_mult); + u32 pwrgate_timer_mult = read32(&pmc->pwrgate_timer_mult); pwrgate_timer_mult |= (0x3 << 0);
/* @@ -71,7 +71,7 @@ void power_enable_cpu_rail(void)
power_ungate_partition(POWER_PARTID_CRAIL);
- uint32_t cntrl = read32(&pmc->cntrl); + u32 cntrl = read32(&pmc->cntrl); cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; cntrl |= PMC_CNTRL_CPUPWRREQ_OE; write32(cntrl, &pmc->cntrl); diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index f0797db..33028e2 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -29,13 +29,13 @@ #include "pmc.h" #include "sdram.h"
-static void sdram_patch(uintptr_t addr, uint32_t value) +static void sdram_patch(uintptr_t addr, u32 value) { if (addr) - writel(value, (uint32_t*)addr); + writel(value, (u32*)addr); }
-static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) +static void writebits(u32 value, u32 *addr, u32 mask) { clrsetbits_le32(addr, mask, (value & mask)); } @@ -392,7 +392,7 @@ static void sdram_patch_bootrom(const struct sdram_params *param, BOOT_ROM_PATCH_CONTROL_OFFSET_MASK) >> BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT); addr = BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS + (addr << 2); - writel(param->BootRomPatchData, (uint32_t *)addr); + writel(param->BootRomPatchData, (u32 *)addr); writel(1, ®s->timing_control); } } @@ -438,7 +438,7 @@ static void sdram_set_dli_trims(const struct sdram_params *param, static void sdram_set_clock_enable_signal(const struct sdram_params *param, struct tegra_emc_regs *regs) { - volatile uint32_t dummy = 0; + volatile u32 dummy = 0; clrbits_le32(®s->pin, (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK | EMC_PIN_CKE_MASK)); /* @@ -519,7 +519,7 @@ static void sdram_set_refresh(const struct sdram_params *param, { /* Insert burst refresh */ if (param->EmcExtraRefreshNum > 0) { - uint32_t refresh_num = (1 << param->EmcExtraRefreshNum) - 1; + u32 refresh_num = (1 << param->EmcExtraRefreshNum) - 1; writebits((EMC_REF_CMD_REFRESH | EMC_REF_NORMAL_ENABLED | (refresh_num << EMC_REF_NUM_SHIFT) | (param->EmcDevSelect << EMC_REF_DEV_SELECTN_SHIFT)), @@ -546,7 +546,7 @@ static void sdram_set_refresh(const struct sdram_params *param, static void sdram_enable_arbiter(const struct sdram_params *param) { /* TODO(hungte) Move values here to standalone header file. */ - uint32_t *AHB_ARBITRATION_XBAR_CTRL = (uint32_t*)(0x6000c000 + 0xe0); + u32 *AHB_ARBITRATION_XBAR_CTRL = (u32*)(0x6000c000 + 0xe0); setbits_le32(AHB_ARBITRATION_XBAR_CTRL, param->AhbArbitrationXbarCtrlMemInitDone << 16); } @@ -612,7 +612,7 @@ void sdram_init(const struct sdram_params *param) sdram_lp0_save_params(param); }
-uint32_t sdram_get_ram_code(void) +u32 sdram_get_ram_code(void) { struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs*)TEGRA_PMC_BASE; return ((readl(&pmc->strapping_opt_a) & diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index fd8074d..19af245 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -26,22 +26,22 @@
struct tegra124_uart { union { - uint32_t thr; // Transmit holding register. - uint32_t rbr; // Receive buffer register. - uint32_t dll; // Divisor latch lsb. + u32 thr; // Transmit holding register. + u32 rbr; // Receive buffer register. + u32 dll; // Divisor latch lsb. }; union { - uint32_t ier; // Interrupt enable register. - uint32_t dlm; // Divisor latch msb. + u32 ier; // Interrupt enable register. + u32 dlm; // Divisor latch msb. }; union { - uint32_t iir; // Interrupt identification register. - uint32_t fcr; // FIFO control register. + u32 iir; // Interrupt identification register. + u32 fcr; // FIFO control register. }; - uint32_t lcr; // Line control register. - uint32_t mcr; // Modem control register. - uint32_t lsr; // Line status register. - uint32_t msr; // Modem status register. + u32 lcr; // Line control register. + u32 mcr; // Modem control register. + u32 lsr; // Line status register. + u32 msr; // Modem status register. } __attribute__ ((packed));
static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr); @@ -51,7 +51,7 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr) { // Use a hardcoded divisor for now. const unsigned divisor = 221; - const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1 + const u8 line_config = UART8250_LCR_WLS_8; // 8n1
tegra124_uart_tx_flush(uart_ptr);
diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 52d11c1..15d3743 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -139,7 +139,7 @@ static unsigned int qup_apps_clk_state[NUM_PORTS] = { };
-static int check_bit_state(uint32_t reg_addr, int bit_num, int val, int us_delay) +static int check_bit_state(u32 reg_addr, int bit_num, int val, int us_delay) { unsigned int count = TIMEOUT_CNT; unsigned int bit_val = ((readl_i(reg_addr) >> bit_num) & 0x01); @@ -171,9 +171,9 @@ static int check_qup_state_valid(struct ipq_spi_slave *ds) */ static int config_spi_state(struct ipq_spi_slave *ds, unsigned int state) { - uint32_t val; + u32 val; int ret; - uint32_t new_state; + u32 new_state;
ret = check_qup_state_valid(ds); if (ret != SUCCESS) @@ -212,7 +212,7 @@ static void spi_set_mode(struct ipq_spi_slave *ds, unsigned int mode) { unsigned int clk_idle_state; unsigned int input_first_mode; - uint32_t val; + u32 val;
switch (mode) { case GSBI_SPI_MODE_0: @@ -274,8 +274,8 @@ static int check_qup_clk_state(unsigned int core_num, int enable) static void CS_change(int port_num, int cs_num, int enable) { unsigned int cs_gpio = cs_gpio_array[port_num][cs_num]; - uint32_t addr = GPIO_IN_OUT_ADDR(cs_gpio); - uint32_t val = readl_i(addr); + u32 addr = GPIO_IN_OUT_ADDR(cs_gpio); + u32 val = readl_i(addr);
val &= (~(1 << GPIO_OUT)); if (!enable) @@ -648,8 +648,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned out_bytes, void *din, unsigned in_bytes) { int ret; - uint8_t* dbuf; - const uint8_t* dobuf; + u8* dbuf; + const u8* dobuf; struct ipq_spi_slave *ds = to_ipq_spi(slave);
/* Assert the chip select */ diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index f7b5d02..eef1be3 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -466,16 +466,16 @@ int uart_can_rx_byte(void) * * Returns the character read from serial port. */ -uint8_t uart_rx_byte(int idx) +u8 uart_rx_byte(int idx) { - uint8_t byte; + u8 byte;
#if 0 /* Not used yet */ while (!uart_can_rx_byte()) { /* wait for incoming data */ } #endif - byte = (uint8_t)(word & 0xff); + byte = (u8)(word & 0xff); word = word >> 8; valid_data--;
diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 60fa55a..44011f5 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -99,8 +99,8 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, * region is aligned such that we don't change dcache policy for other * stuff inadvertently. */ - uint32_t lower = ALIGN_DOWN(lcdbase, MiB); - uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); + u32 lower = ALIGN_DOWN(lcdbase, MiB); + u32 upper = ALIGN_UP(lcdbase + fb_size, MiB);
dcache_clean_invalidate_by_mva((void *)lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); @@ -149,7 +149,7 @@ struct chip_operations soc_samsung_exynos5250_ops = {
void exynos5250_config_l2_cache(void) { - uint32_t val; + u32 val;
/* * Bit 9 - L2 tag RAM setup (1 cycle) diff --git a/src/soc/samsung/exynos5250/i2c.c b/src/soc/samsung/exynos5250/i2c.c index 1e526d6..980e69c 100644 --- a/src/soc/samsung/exynos5250/i2c.c +++ b/src/soc/samsung/exynos5250/i2c.c @@ -29,16 +29,16 @@
struct __attribute__ ((packed)) i2c_regs { - uint8_t con; - uint8_t _1[3]; - uint8_t stat; - uint8_t _2[3]; - uint8_t add; - uint8_t _3[3]; - uint8_t ds; - uint8_t _4[3]; - uint8_t lc; - uint8_t _5[3]; + u8 con; + u8 _1[3]; + u8 stat; + u8 _2[3]; + u8 add; + u8 _3[3]; + u8 ds; + u8 _4[3]; + u8 lc; + u8 _5[3]; };
struct s3c24x0_i2c_bus { @@ -169,7 +169,7 @@ static int i2c_wait_for_int(struct i2c_regs *regs)
static int i2c_send_stop(struct i2c_regs *regs) { - uint8_t mode = readb(®s->stat) & (I2cStatModeMask); + u8 mode = readb(®s->stat) & (I2cStatModeMask); writeb(mode | I2cStatEnable, ®s->stat); i2c_clear_int(regs); return i2c_wait_for_idle(regs); @@ -178,7 +178,7 @@ static int i2c_send_stop(struct i2c_regs *regs) static int i2c_send_start(struct i2c_regs *regs, int read, int chip) { writeb(chip << 1, ®s->ds); - uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; + u8 mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; writeb(mode | I2cStatStartStop | I2cStatEnable, ®s->stat); i2c_clear_int(regs);
@@ -193,7 +193,7 @@ static int i2c_send_start(struct i2c_regs *regs, int read, int chip) return 0; }
-static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) +static int i2c_xmit_buf(struct i2c_regs *regs, u8 *data, int len) { ASSERT(len);
@@ -216,7 +216,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) return 0; }
-static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) +static int i2c_recv_buf(struct i2c_regs *regs, u8 *data, int len) { ASSERT(len);
diff --git a/src/soc/samsung/exynos5250/mct.c b/src/soc/samsung/exynos5250/mct.c index bbb90e4..aacd242 100644 --- a/src/soc/samsung/exynos5250/mct.c +++ b/src/soc/samsung/exynos5250/mct.c @@ -21,10 +21,10 @@ #include <arch/io.h> #include "clk.h"
-uint64_t mct_raw_value(void) +u64 mct_raw_value(void) { - uint64_t upper = readl(&exynos_mct->g_cnt_u); - uint64_t lower = readl(&exynos_mct->g_cnt_l); + u64 upper = readl(&exynos_mct->g_cnt_u); + u64 lower = readl(&exynos_mct->g_cnt_l);
return (upper << 32) | lower; } diff --git a/src/soc/samsung/exynos5250/monotonic_timer.c b/src/soc/samsung/exynos5250/monotonic_timer.c index 89ac416..f78be18 100644 --- a/src/soc/samsung/exynos5250/monotonic_timer.c +++ b/src/soc/samsung/exynos5250/monotonic_timer.c @@ -22,7 +22,7 @@
#include "clk.h"
-static const uint32_t clocks_per_usec = MCT_HZ/1000000; +static const u32 clocks_per_usec = MCT_HZ/1000000;
void timer_monotonic_get(struct mono_time *mt) { diff --git a/src/soc/samsung/exynos5250/power.c b/src/soc/samsung/exynos5250/power.c index 7d94712..421ec03 100644 --- a/src/soc/samsung/exynos5250/power.c +++ b/src/soc/samsung/exynos5250/power.c @@ -62,7 +62,7 @@ void power_enable_hw_thermal_trip(void) setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); }
-uint32_t power_read_reset_status(void) +u32 power_read_reset_status(void) { return exynos_power->inform1; } diff --git a/src/soc/samsung/exynos5250/spi.c b/src/soc/samsung/exynos5250/spi.c index 33ec698..054c015 100644 --- a/src/soc/samsung/exynos5250/spi.c +++ b/src/soc/samsung/exynos5250/spi.c @@ -49,7 +49,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo, writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
while (in_bytes) { - uint32_t spi_sts; + u32 spi_sts; int temp;
spi_sts = readl(®s->spi_sts); diff --git a/src/soc/samsung/exynos5250/wakeup.c b/src/soc/samsung/exynos5250/wakeup.c index b7161cf..6dae827 100644 --- a/src/soc/samsung/exynos5250/wakeup.c +++ b/src/soc/samsung/exynos5250/wakeup.c @@ -34,7 +34,7 @@ void wakeup(void)
int get_wakeup_state(void) { - uint32_t status = power_read_reset_status(); + u32 status = power_read_reset_status();
/* DIDLE/LPA can be resumed without clock reset (ex, bootblock), * and SLEEP requires resetting clock (should be done in ROM stage). diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index e8649a0..7b35dc6 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -113,8 +113,8 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, * region is aligned such that we don't change dcache policy for other * stuff inadvertently. */ - uint32_t lower = ALIGN_DOWN(lcdbase, MiB); - uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); + u32 lower = ALIGN_DOWN(lcdbase, MiB); + u32 upper = ALIGN_UP(lcdbase + fb_size, MiB);
dcache_clean_invalidate_by_mva((void *)lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); @@ -124,7 +124,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase,
static void tps65090_thru_ec_fet_disable(int index) { - uint8_t value = 0; + u8 value = 0;
if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) { printk(BIOS_ERR, diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 49875d7..09d9afc 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -32,49 +32,49 @@
struct __attribute__ ((packed)) i2c_regs { - uint8_t con; - uint8_t _1[3]; - uint8_t stat; - uint8_t _2[3]; - uint8_t add; - uint8_t _3[3]; - uint8_t ds; - uint8_t _4[3]; - uint8_t lc; - uint8_t _5[3]; + u8 con; + u8 _1[3]; + u8 stat; + u8 _2[3]; + u8 add; + u8 _3[3]; + u8 ds; + u8 _4[3]; + u8 lc; + u8 _5[3]; };
struct __attribute__ ((packed)) hsi2c_regs { - uint32_t usi_ctl; - uint32_t usi_fifo_ctl; - uint32_t usi_trailing_ctl; - uint32_t usi_clk_ctl; - uint32_t usi_clk_slot; - uint32_t spi_ctl; - uint32_t uart_ctl; - uint32_t res1; - uint32_t usi_int_en; - uint32_t usi_int_stat; - uint32_t modem_stat; - uint32_t error_stat; - uint32_t usi_fifo_stat; - uint32_t usi_txdata; - uint32_t usi_rxdata; - uint32_t res2; - uint32_t i2c_conf; - uint32_t i2c_auto_conf; - uint32_t i2c_timeout; - uint32_t i2c_manual_cmd; - uint32_t i2c_trans_status; - uint32_t i2c_timing_hs1; - uint32_t i2c_timing_hs2; - uint32_t i2c_timing_hs3; - uint32_t i2c_timing_fs1; - uint32_t i2c_timing_fs2; - uint32_t i2c_timing_fs3; - uint32_t i2c_timing_sla; - uint32_t i2c_addr; + u32 usi_ctl; + u32 usi_fifo_ctl; + u32 usi_trailing_ctl; + u32 usi_clk_ctl; + u32 usi_clk_slot; + u32 spi_ctl; + u32 uart_ctl; + u32 res1; + u32 usi_int_en; + u32 usi_int_stat; + u32 modem_stat; + u32 error_stat; + u32 usi_fifo_stat; + u32 usi_txdata; + u32 usi_rxdata; + u32 res2; + u32 i2c_conf; + u32 i2c_auto_conf; + u32 i2c_timeout; + u32 i2c_manual_cmd; + u32 i2c_trans_status; + u32 i2c_timing_hs1; + u32 i2c_timing_hs2; + u32 i2c_timing_hs3; + u32 i2c_timing_fs1; + u32 i2c_timing_fs2; + u32 i2c_timing_fs3; + u32 i2c_timing_sla; + u32 i2c_addr; }; check_member(hsi2c_regs, i2c_addr, 0x70);
@@ -270,7 +270,7 @@ static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle, * temp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) * temp1 = (TSCLK_L + TSCLK_H + 2) */ - uint32_t flt_cycle = (readl(®s->i2c_conf) >> 16) & 0x7; + u32 flt_cycle = (readl(®s->i2c_conf) >> 16) & 0x7; int temp = (clkin / op_clk) - 8 - 2 * flt_cycle;
// CLK_DIV max is 256. @@ -295,19 +295,19 @@ static void hsi2c_ch_init(struct i2c_bus *i2c, unsigned int frequency) if (hsi2c_get_clk_details(i2c, &div, &cycle, frequency)) return;
- uint32_t sr_release; + u32 sr_release; sr_release = cycle;
- uint32_t scl_l, scl_h, start_su, start_hd, stop_su; + u32 scl_l, scl_h, start_su, start_hd, stop_su; scl_l = scl_h = start_su = start_hd = stop_su = cycle / 2;
- uint32_t data_su, data_hd; + u32 data_su, data_hd; data_su = data_hd = cycle / 4;
- uint32_t timing_fs1 = start_su << 24 | start_hd << 16 | stop_su << 8; - uint32_t timing_fs2 = data_su << 24 | scl_l << 8 | scl_h << 0; - uint32_t timing_fs3 = div << 16 | sr_release << 0; - uint32_t timing_sla = data_hd << 0; + u32 timing_fs1 = start_su << 24 | start_hd << 16 | stop_su << 8; + u32 timing_fs2 = data_su << 24 | scl_l << 8 | scl_h << 0; + u32 timing_fs3 = div << 16 | sr_release << 0; + u32 timing_sla = data_hd << 0;
// Currently operating in fast speed mode. writel(timing_fs1, ®s->i2c_timing_fs1); @@ -386,7 +386,7 @@ void i2c_init(unsigned bus, int speed, int slaveadd) */ static int hsi2c_check_transfer(struct hsi2c_regs *regs) { - uint32_t status = read32(®s->i2c_trans_status); + u32 status = read32(®s->i2c_trans_status); if (status & (Hsi2cTransAbort | Hsi2cNoDevAck | Hsi2cNoDev | Hsi2cTimeoutAuto)) { if (status & Hsi2cTransAbort) @@ -429,7 +429,7 @@ static int hsi2c_wait_for_transfer(struct hsi2c_regs *i2c) return 0; }
-static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len) +static int hsi2c_senddata(struct hsi2c_regs *regs, const u8 *data, int len) { while (!hsi2c_check_transfer(regs) && len) { if (!(read32(®s->usi_fifo_stat) & Hsi2cTxFifoFull)) { @@ -440,7 +440,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len) return len ? -1 : 0; }
-static int hsi2c_recvdata(struct hsi2c_regs *regs, uint8_t *data, int len) +static int hsi2c_recvdata(struct hsi2c_regs *regs, u8 *data, int len) { while (!hsi2c_check_transfer(regs) && len) { if (!(read32(®s->usi_fifo_stat) & Hsi2cRxFifoEmpty)) { @@ -453,7 +453,7 @@ static int hsi2c_recvdata(struct hsi2c_regs *regs, uint8_t *data, int len)
static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) { - const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster; + const u32 usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster;
write32(HSI2C_SLV_ADDR_MAS(seg->chip), ®s->i2c_addr);
@@ -464,7 +464,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop) * clear. We may need to switch to manual mode to really get the * behavior we want. */ - uint32_t autoconf = + u32 autoconf = seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans;
if (seg->read) { @@ -565,7 +565,7 @@ static int i2c_wait_for_int(struct i2c_regs *regs)
static int i2c_send_stop(struct i2c_regs *regs) { - uint8_t mode = readb(®s->stat) & (I2cStatModeMask); + u8 mode = readb(®s->stat) & (I2cStatModeMask); writeb(mode | I2cStatEnable, ®s->stat); i2c_clear_int(regs); return i2c_wait_for_idle(regs); @@ -574,7 +574,7 @@ static int i2c_send_stop(struct i2c_regs *regs) static int i2c_send_start(struct i2c_regs *regs, int read, int chip) { writeb(chip << 1, ®s->ds); - uint8_t mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; + u8 mode = read ? I2cStatMasterRecv : I2cStatMasterXmit; writeb(mode | I2cStatStartStop | I2cStatEnable, ®s->stat); i2c_clear_int(regs);
@@ -589,7 +589,7 @@ static int i2c_send_start(struct i2c_regs *regs, int read, int chip) return 0; }
-static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) +static int i2c_xmit_buf(struct i2c_regs *regs, u8 *data, int len) { ASSERT(len);
@@ -612,7 +612,7 @@ static int i2c_xmit_buf(struct i2c_regs *regs, uint8_t *data, int len) return 0; }
-static int i2c_recv_buf(struct i2c_regs *regs, uint8_t *data, int len) +static int i2c_recv_buf(struct i2c_regs *regs, u8 *data, int len) { ASSERT(len);
diff --git a/src/soc/samsung/exynos5420/mct.c b/src/soc/samsung/exynos5420/mct.c index bbb90e4..aacd242 100644 --- a/src/soc/samsung/exynos5420/mct.c +++ b/src/soc/samsung/exynos5420/mct.c @@ -21,10 +21,10 @@ #include <arch/io.h> #include "clk.h"
-uint64_t mct_raw_value(void) +u64 mct_raw_value(void) { - uint64_t upper = readl(&exynos_mct->g_cnt_u); - uint64_t lower = readl(&exynos_mct->g_cnt_l); + u64 upper = readl(&exynos_mct->g_cnt_u); + u64 lower = readl(&exynos_mct->g_cnt_l);
return (upper << 32) | lower; } diff --git a/src/soc/samsung/exynos5420/monotonic_timer.c b/src/soc/samsung/exynos5420/monotonic_timer.c index 89ac416..f78be18 100644 --- a/src/soc/samsung/exynos5420/monotonic_timer.c +++ b/src/soc/samsung/exynos5420/monotonic_timer.c @@ -22,7 +22,7 @@
#include "clk.h"
-static const uint32_t clocks_per_usec = MCT_HZ/1000000; +static const u32 clocks_per_usec = MCT_HZ/1000000;
void timer_monotonic_get(struct mono_time *mt) { diff --git a/src/soc/samsung/exynos5420/power.c b/src/soc/samsung/exynos5420/power.c index 7d94712..421ec03 100644 --- a/src/soc/samsung/exynos5420/power.c +++ b/src/soc/samsung/exynos5420/power.c @@ -62,7 +62,7 @@ void power_enable_hw_thermal_trip(void) setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP); }
-uint32_t power_read_reset_status(void) +u32 power_read_reset_status(void) { return exynos_power->inform1; } diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 41a57ab..dfc736b 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -63,21 +63,21 @@ * kernel (EXYNOS5420_PA_SYSRAM_NS = 0x02073000). */ volatile struct exynos5420_cpu_states { - uint32_t _reserved[2]; /* RESV, +0x00 */ - uint32_t resume_address; /* REG0, +0x08 */ - uint32_t resume_flag; /* REG1, +0x0C */ - uint32_t _reg2; /* REG2, +0x10 */ - uint32_t _reg3; /* REG3, +0x14 */ - uint32_t switch_address; /* REG4, +0x18, cluster switching */ - uint32_t hotplug_address; /* REG5, +0x1C, core hotplug */ - uint32_t _reg6; /* REG6, +0x20 */ - uint32_t c2_address; /* REG7, +0x24, C2 state change */ + u32 _reserved[2]; /* RESV, +0x00 */ + u32 resume_address; /* REG0, +0x08 */ + u32 resume_flag; /* REG1, +0x0C */ + u32 _reg2; /* REG2, +0x10 */ + u32 _reg3; /* REG3, +0x14 */ + u32 switch_address; /* REG4, +0x18, cluster switching */ + u32 hotplug_address; /* REG5, +0x1C, core hotplug */ + u32 _reg6; /* REG6, +0x20 */ + u32 c2_address; /* REG7, +0x24, C2 state change */
/* Managed per core status for active cluster, offset: +0x28~0x38 */ - uint32_t cpu_states[4]; + u32 cpu_states[4];
/* Managed per core GIC status for active cluster, offset: 0x38~0x48 */ - uint32_t cpu_gic_states[4]; + u32 cpu_gic_states[4]; } *exynos_cpu_states = (volatile struct exynos5420_cpu_states*)0x02073000;
/* When leaving core handlers and jump to hot-plug address (or cluster @@ -91,14 +91,14 @@ inline static void jump_bx(void *address) }
/* Extracts arbitrary bits from a 32-bit unsigned int. */ -inline static uint32_t get_bits(uint32_t value, uint32_t start, uint32_t len) +inline static u32 get_bits(u32 value, u32 start, u32 len) { return ((value << (sizeof(value) * 8 - len - start)) >> (sizeof(value) * 8 - len)); }
/* Waits the referenced address to be ready (non-zero) and then jump into it. */ -static void wait_and_jump(volatile uint32_t* reference) +static void wait_and_jump(volatile u32* reference) { while (!*reference) { wfe(); @@ -109,7 +109,7 @@ static void wait_and_jump(volatile uint32_t* reference) /* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ static void configure_l2ctlr(void) { - uint32_t val; + u32 val;
val = read_l2ctlr(); val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); @@ -121,7 +121,7 @@ static void configure_l2ctlr(void) /* Configures L2 Auxiliary Control Register for Cortex A15. */ static void configure_l2actlr(void) { - uint32_t val; + u32 val;
val = read_l2actlr(); val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | @@ -146,7 +146,7 @@ static void init_exynos_cpu_states(void) { */ static void enable_smp(void) { - uint32_t actlr, val; + u32 actlr, val;
/* Enable SMP mode */ actlr = read_actlr(); @@ -196,7 +196,7 @@ static void core_start_execution(void) /* The entry point for hotplug-in and cluster switching. */ static void low_power_start(void) { - uint32_t sctlr, reg_val; + u32 sctlr, reg_val;
/* On warm reset, because iRAM is not cleared, all cores will enter * low_power_start, not the initial address. So we need to check reset @@ -248,7 +248,7 @@ static void low_power_start(void) /* Callback to shutdown a core, safe to be set as hot-plug address. */ static void power_down_core(void) { - uint32_t mpidr, core_id; + u32 mpidr, core_id;
/* MPIDR: 0~2=ID, 8~11=cluster. On Exynos 5420, cluster will be only 0 * or 1. */ diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 36742a7..89ed639 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -70,10 +70,10 @@ static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
static void spi_sw_reset(struct exynos_spi *regs, int word) { - const uint32_t orig_mode_cfg = readl(®s->mode_cfg); - uint32_t mode_cfg = orig_mode_cfg; - const uint32_t orig_swap_cfg = readl(®s->swap_cfg); - uint32_t swap_cfg = orig_swap_cfg; + const u32 orig_mode_cfg = readl(®s->mode_cfg); + u32 mode_cfg = orig_mode_cfg; + const u32 orig_swap_cfg = readl(®s->swap_cfg); + u32 swap_cfg = orig_swap_cfg;
mode_cfg &= ~(SPI_MODE_CH_WIDTH_MASK | SPI_MODE_BUS_WIDTH_MASK); if (word) { @@ -161,12 +161,12 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out, writel(packets | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
while (out_bytes || in_bytes) { - uint32_t spi_sts = readl(®s->spi_sts); + u32 spi_sts = readl(®s->spi_sts); int rx_lvl = ((spi_sts >> 15) & 0x1ff); int tx_lvl = ((spi_sts >> 6) & 0x1ff);
if (tx_lvl < 32 && tx_lvl < out_bytes) { - uint32_t data = 0xffffffff; + u32 data = 0xffffffff;
if (outb) { memcpy(&data, outb, width); @@ -178,7 +178,7 @@ static void spi_transfer(struct exynos_spi *regs, void *in, const void *out, }
if (rx_lvl >= width) { - uint32_t data = readl(®s->rx_data); + u32 data = readl(®s->rx_data);
if (inb) { memcpy(inb, &data, width); @@ -206,8 +206,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytes_out, bytes_out -= min_size; bytes_in -= min_size;
- din = (uint8_t *)din + min_size; - dout = (const uint8_t *)dout + min_size; + din = (u8 *)din + min_size; + dout = (const u8 *)dout + min_size; }
if (bytes_in) @@ -224,8 +224,8 @@ void spi_release_bus(struct spi_slave *slave) setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); }
-static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len, - uint32_t off) +static int exynos_spi_read(struct spi_slave *slave, void *dest, u32 len, + u32 off) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; u32 command; diff --git a/src/soc/samsung/exynos5420/wakeup.c b/src/soc/samsung/exynos5420/wakeup.c index a240717..e951ebd 100644 --- a/src/soc/samsung/exynos5420/wakeup.c +++ b/src/soc/samsung/exynos5420/wakeup.c @@ -36,7 +36,7 @@ void wakeup(void)
int get_wakeup_state(void) { - uint32_t status = power_read_reset_status(); + u32 status = power_read_reset_status();
/* DIDLE/LPA can be resumed without clock reset (ex, bootblock), * and SLEEP requires resetting clock (should be done in ROM stage). diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 1b9b689..79c8934 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -140,7 +140,7 @@ int acpi_is_wakeup_early(void)
unsigned long get_top_of_ram(void) { - uint32_t xdata = 0; + u32 xdata = 0; int xnvram_pos = 0xf8, xi; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index be8aa69..96a7bab 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -49,7 +49,7 @@ int acpi_get_sleep_type(void) } #endif
-void backup_top_of_ram(uint64_t ramtop) +void backup_top_of_ram(u64 ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ @@ -163,7 +163,7 @@ void hudson_enable(device_t dev) #if CONFIG_HAVE_ACPI_RESUME unsigned long get_top_of_ram(void) { - uint32_t xdata = 0; + u32 xdata = 0; int xnvram_pos = 0xf8, xi; if (acpi_get_sleep_type() != 3) return 0; diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c index 1d58afe..b1d6069 100644 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ b/src/southbridge/amd/agesa/hudson/smi.c @@ -18,7 +18,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) /** Set the EOS bit and enable SMI generation from southbridge */ void hudson_enable_smi_generation(void) { - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + u32 reg = smi_read32(SMI_REG_SMITRIG0); reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c index 6076cd4..13b2f8f 100644 --- a/src/southbridge/amd/agesa/hudson/smi_util.c +++ b/src/southbridge/amd/agesa/hudson/smi_util.c @@ -11,10 +11,10 @@
#define HUDSON_SMI_ACPI_COMMAND 75
-static void configure_smi(uint8_t smi_num, uint8_t mode) +static void configure_smi(u8 smi_num, u8 mode) { - uint8_t reg32_offset, bit_offset; - uint32_t reg32; + u8 reg32_offset, bit_offset; + u32 reg32;
/* SMI sources range from [0:149] */ if (smi_num > 149) { @@ -40,9 +40,9 @@ static void configure_smi(uint8_t smi_num, uint8_t mode) * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. * @param level SMI_LVL_LOW or SMI_LVL_HIGH */ -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) +void hudson_configure_gevent_smi(u8 gevent, u8 mode, u8 level) { - uint32_t reg32; + u32 reg32; /* GEVENT pins range from [0:23] */ if (gevent > 23) { printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); @@ -60,7 +60,7 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) }
/** Disable events from given GEVENT pin */ -void hudson_disable_gevent_smi(uint8_t gevent) +void hudson_disable_gevent_smi(u8 gevent) { /* GEVENT pins range from [0:23] */ if (gevent > 23) { diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index d1b661b..522e462 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -26,7 +26,7 @@ enum smi_source { static void hudson_apmc_smi_handler(void) { u32 reg32; - const uint8_t cmd = inb(ACPI_SMI_CTL_PORT); + const u8 cmd = inb(ACPI_SMI_CTL_PORT);
switch (cmd) { case ACPI_SMI_CMD_ENABLE: @@ -52,7 +52,7 @@ int southbridge_io_trap_handler(int smif)
static void process_smi_sci(void) { - const uint32_t status = smi_read32(0x10); + const u32 status = smi_read32(0x10);
/* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x10, status); @@ -60,8 +60,8 @@ static void process_smi_sci(void)
static void process_gpe_smi(void) { - const uint32_t status = smi_read32(0x80); - const uint32_t gevent_mask = (1 << 24) - 1; + const u32 status = smi_read32(0x80); + const u32 gevent_mask = (1 << 24) - 1;
/* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { @@ -76,7 +76,7 @@ static void process_gpe_smi(void)
static void process_smi_0x84(void) { - const uint32_t status = smi_read32(0x84); + const u32 status = smi_read32(0x84);
/* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x84, status); @@ -84,7 +84,7 @@ static void process_smi_0x84(void)
static void process_smi_0x88(void) { - const uint32_t status = smi_read32(0x88); + const u32 status = smi_read32(0x88);
if (status & SMI_0x88_ACPI_COMMAND) { /* Command received via ACPI SMI command port */ @@ -96,7 +96,7 @@ static void process_smi_0x88(void)
static void process_smi_0x8c(void) { - const uint32_t status = smi_read32(0x8c); + const u32 status = smi_read32(0x8c);
/* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x8c, status); @@ -104,7 +104,7 @@ static void process_smi_0x8c(void)
static void process_smi_0x90(void) { - const uint32_t status = smi_read32(0x90); + const u32 status = smi_read32(0x90);
/* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x90, status); @@ -112,7 +112,7 @@ static void process_smi_0x90(void)
void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { - const uint16_t smi_src = smi_read16(0x94); + const u16 smi_src = smi_read16(0x94);
if (smi_src & SMI_SOURCE_SCI) process_smi_sci(); @@ -130,7 +130,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
void southbridge_smi_set_eos(void) { - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + u32 reg = smi_read32(SMI_REG_SMITRIG0); reg |= SMITRG0_EOS; smi_write32(SMI_REG_SMITRIG0, reg); } diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 735ab7e..d500524 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -51,19 +51,19 @@ static int bus_claimed = 0;
static u32 spibar;
-static inline uint8_t spi_read(uint8_t reg) +static inline u8 spi_read(u8 reg) { return read8(spibar + reg); }
-static inline void spi_write(uint8_t reg, uint8_t val) +static inline void spi_write(u8 reg, u8 val) { write8(spibar + reg, val); }
static void reset_internal_fifo_pointer(void) { - uint8_t reg8; + u8 reg8;
do { reg8 = spi_read(SPI_REG_CNTRL02); @@ -74,7 +74,7 @@ static void reset_internal_fifo_pointer(void)
static void execute_command(void) { - uint8_t reg8; + u8 reg8;
reg8 = spi_read(SPI_REG_CNTRL02); reg8 |= CNTRL02_EXEC_OPCODE; @@ -135,7 +135,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
reset_internal_fifo_pointer(); for (count = 0; count < bytesout; count++, dout++) { - spi_write(SPI_REG_FIFO, *(uint8_t *)dout); + spi_write(SPI_REG_FIFO, *(u8 *)dout); }
reset_internal_fifo_pointer(); @@ -149,7 +149,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
reset_internal_fifo_pointer(); for (count = 0; count < bytesin; count++, din++) { - *(uint8_t *)din = spi_read(SPI_REG_FIFO); + *(u8 *)din = spi_read(SPI_REG_FIFO); }
return 0; diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 6d0ce26..ea2c10d 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -32,7 +32,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); }
-static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(device_t dev, u8 val) { unsigned device; struct resource *res; @@ -44,7 +44,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) }
-static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(device_t dev, u8 address) { unsigned device; struct resource *res; @@ -55,7 +55,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); }
-static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(device_t dev, u8 address, u8 val) { unsigned device; struct resource *res; @@ -66,7 +66,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) return do_smbus_write_byte(res->base, device, address, val); }
-static int lsmbus_block_read(device_t dev, uint8_t cmd, u8 bytes, u8 *buffer) +static int lsmbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer) { unsigned device; struct resource *res; @@ -77,7 +77,8 @@ static int lsmbus_block_read(device_t dev, uint8_t cmd, u8 bytes, u8 *buffer) return do_smbus_block_read(res->base, device, cmd, bytes, buffer); }
-static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buffer) +static int lsmbus_block_write(device_t dev, u8 cmd, u8 bytes, + const u8 *buffer) { unsigned device; struct resource *res; @@ -95,8 +96,8 @@ unsigned pm_base;
static void acpi_init(struct device *dev) { - uint8_t byte; - uint16_t pm10_bar; + u8 byte; + u16 pm10_bar; int on;
#if 0 @@ -188,7 +189,7 @@ static void acpi_read_resources(device_t dev)
static void acpi_enable_resources(device_t dev) { - uint8_t byte; + u8 byte; /* Enable the generic pci resources */ pci_dev_enable_resources(dev);
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c index 2707ca6..2cd4a92 100644 --- a/src/southbridge/amd/amd8111/amd8111.c +++ b/src/southbridge/amd/amd8111/amd8111.c @@ -35,7 +35,7 @@ void amd8111_enable(device_t dev) if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) || (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) { - uint32_t id; + u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) { return; diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index ece99ed..51fadfe 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -20,7 +20,7 @@ static unsigned get_sbdn(unsigned bus) static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) { device_t dev; - uint8_t byte; + u8 byte;
dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI /* enable cf9 */ diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index e236286..a8ebf8e 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -5,7 +5,7 @@ static void enable_smbus(void) { device_t dev; - uint8_t enable; + u8 enable;
dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c index ef0cee1..8702490 100644 --- a/src/southbridge/amd/amd8111/ide.c +++ b/src/southbridge/amd/amd8111/ide.c @@ -9,8 +9,8 @@ static void ide_init(struct device *dev) { struct southbridge_amd_amd8111_config *conf; /* Enable ide devices so the linux ide driver will work */ - uint16_t word; - uint8_t byte; + u16 word; + u8 byte; conf = dev->chip_info;
word = pci_read_config16(dev, 0x40); diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 718b40b..db8b1e6 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -34,7 +34,7 @@ static void enable_hpet(struct device *dev)
static void lpc_init(struct device *dev) { - uint8_t byte; + u8 byte; int nmi_option;
/* IO APIC initialization */ diff --git a/src/southbridge/amd/amd8111/pci.c b/src/southbridge/amd/amd8111/pci.c index f882490..facc11f 100644 --- a/src/southbridge/amd/amd8111/pci.c +++ b/src/southbridge/amd/amd8111/pci.c @@ -9,7 +9,7 @@ static void pci_init(struct device *dev) {
/* Enable pci error detecting */ - uint32_t dword; + u32 dword;
/* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/amd/amd8131-disable/bridge.c b/src/southbridge/amd/amd8131-disable/bridge.c index e90f497..3b8222e 100644 --- a/src/southbridge/amd/amd8131-disable/bridge.c +++ b/src/southbridge/amd/amd8131-disable/bridge.c @@ -47,8 +47,8 @@ static unsigned int amd8131_scan_bus(device_t bus, unsigned int max)
static void amd8131_enable(device_t dev) { - uint32_t buses; - uint16_t cr; + u32 buses; + u16 cr;
/* Clear all status bits and turn off memory, I/O and master enables. */ pci_write_config16(dev, PCI_COMMAND, 0x0000); @@ -89,7 +89,7 @@ static const struct pci_driver pcix_driver __pci_driver = {
static void ioapic_enable(device_t dev) { - uint32_t value; + u32 value; value = pci_read_config32(dev, 0x44); if (dev->enabled) { value |= ((1 << 1) | (1 << 0)); diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index e638fae..cd8078e 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -275,9 +275,9 @@ static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max)
static void amd8131_pcix_init(device_t dev) { - uint32_t dword; - uint16_t word; - uint8_t byte; + u32 dword; + u16 word; + u8 byte; int nmi_option;
/* Enable memory write and invalidate ??? */ @@ -400,7 +400,7 @@ static const struct pci_driver pcix_driver __pci_driver = {
static void ioapic_enable(device_t dev) { - uint32_t value; + u32 value;
value = pci_read_config32(dev, 0x44); if (dev->enabled) { diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index eecb11b..94a0234 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -205,8 +205,8 @@ static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max)
static void amd8132_pcix_init(device_t dev) { - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte; unsigned chip_rev;
/* Find the revision of the 8132 */ @@ -364,7 +364,7 @@ static const struct pci_driver pcix_driver __pci_driver = {
static void ioapic_enable(device_t dev) { - uint32_t value; + u32 value;
value = pci_read_config32(dev, 0x44); if (dev->enabled) { @@ -376,7 +376,7 @@ static void ioapic_enable(device_t dev) } static void amd8132_ioapic_init(device_t dev) { - uint32_t dword; + u32 dword; unsigned chip_rev;
/* Find the revision of the 8132 */ diff --git a/src/southbridge/amd/amd8151/agp3.c b/src/southbridge/amd/amd8151/agp3.c index 3572fae..8f4db7f 100644 --- a/src/southbridge/amd/amd8151/agp3.c +++ b/src/southbridge/amd/amd8151/agp3.c @@ -26,7 +26,7 @@
static void agp3bridge_init(device_t dev) { - uint8_t byte; + u8 byte;
/* Enable BM, MEM and IO */ byte = pci_read_config32(dev, 0x04); @@ -52,7 +52,7 @@ static const struct pci_driver agp3bridge_driver __pci_driver = {
static void agp3dev_enable(device_t dev) { - uint32_t value; + u32 value;
/* AGP enable */ value = pci_read_config32(dev, 0xa8); diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c index 75a3fb9..dcc8e76 100644 --- a/src/southbridge/amd/cimx/sb700/lpc.c +++ b/src/southbridge/amd/cimx/sb700/lpc.c @@ -27,7 +27,7 @@ #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5
-void backup_top_of_ram(uint64_t ramtop) +void backup_top_of_ram(u64 ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 9ddcf8f..7161024 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -37,7 +37,7 @@ int acpi_get_sleep_type(void) #endif
#ifndef __PRE_RAM__ -void backup_top_of_ram(uint64_t ramtop) +void backup_top_of_ram(u64 ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index ab1b640..4d58976 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -151,7 +151,7 @@ static struct FLASH_DEVICE FlashInitTable[] = {
#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
-static uint32_t FlashPort[] = { +static u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c index 4a2e1b4..9e3e2a4 100644 --- a/src/southbridge/amd/cs5535/early_setup.c +++ b/src/southbridge/amd/cs5535/early_setup.c @@ -79,7 +79,7 @@ static void cs5535_setup_iobase(void)
static void cs5535_setup_gpio(void) { - uint32_t val; + u32 val;
/* setup GPIO pins 14/15 for SDA/SCL */ val = (1<<14 | 1<<15); diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index e6ef8ad..9759e26 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -108,7 +108,7 @@ static void cs5536_setup_power_button(void)
static void cs5536_setup_gpio(void) { - uint32_t val; + u32 val;
/* setup GPIO pins 14/15 for SDA/SCL */ val = GPIOL_15_SET | GPIOL_14_SET; diff --git a/src/southbridge/amd/cs5536/ide.c b/src/southbridge/amd/cs5536/ide.c index 55c38cc..2fa5b39 100644 --- a/src/southbridge/amd/cs5536/ide.c +++ b/src/southbridge/amd/cs5536/ide.c @@ -34,7 +34,7 @@
static void ide_init(struct device *dev) { - uint32_t ide_cfg; + u32 ide_cfg;
printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); /* GPIO and IRQ setup are handled in the main chipset code. */ diff --git a/src/southbridge/amd/pi/avalon/early_setup.c b/src/southbridge/amd/pi/avalon/early_setup.c index 039df20..26e364c 100644 --- a/src/southbridge/amd/pi/avalon/early_setup.c +++ b/src/southbridge/amd/pi/avalon/early_setup.c @@ -142,7 +142,7 @@ int acpi_is_wakeup_early(void)
unsigned long get_top_of_ram(void) { - uint32_t xdata = 0; + u32 xdata = 0; int xnvram_pos = 0xf8, xi; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); diff --git a/src/southbridge/amd/pi/avalon/hudson.c b/src/southbridge/amd/pi/avalon/hudson.c index 84eaf30..78118d7 100644 --- a/src/southbridge/amd/pi/avalon/hudson.c +++ b/src/southbridge/amd/pi/avalon/hudson.c @@ -48,7 +48,7 @@ int acpi_get_sleep_type(void) } #endif
-void backup_top_of_ram(uint64_t ramtop) +void backup_top_of_ram(u64 ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xf8, i; /* temp */ @@ -116,7 +116,7 @@ void hudson_enable(device_t dev) #if CONFIG_HAVE_ACPI_RESUME unsigned long get_top_of_ram(void) { - uint32_t xdata = 0; + u32 xdata = 0; int xnvram_pos = 0xf8, xi; if (acpi_get_sleep_type() != 3) return 0; diff --git a/src/southbridge/amd/pi/avalon/smi.c b/src/southbridge/amd/pi/avalon/smi.c index 1d58afe..b1d6069 100644 --- a/src/southbridge/amd/pi/avalon/smi.c +++ b/src/southbridge/amd/pi/avalon/smi.c @@ -18,7 +18,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) /** Set the EOS bit and enable SMI generation from southbridge */ void hudson_enable_smi_generation(void) { - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + u32 reg = smi_read32(SMI_REG_SMITRIG0); reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ reg |= SMITRG0_EOS; /* Set EOS bit */ smi_write32(SMI_REG_SMITRIG0, reg); diff --git a/src/southbridge/amd/pi/avalon/smi_util.c b/src/southbridge/amd/pi/avalon/smi_util.c index 6076cd4..13b2f8f 100644 --- a/src/southbridge/amd/pi/avalon/smi_util.c +++ b/src/southbridge/amd/pi/avalon/smi_util.c @@ -11,10 +11,10 @@
#define HUDSON_SMI_ACPI_COMMAND 75
-static void configure_smi(uint8_t smi_num, uint8_t mode) +static void configure_smi(u8 smi_num, u8 mode) { - uint8_t reg32_offset, bit_offset; - uint32_t reg32; + u8 reg32_offset, bit_offset; + u32 reg32;
/* SMI sources range from [0:149] */ if (smi_num > 149) { @@ -40,9 +40,9 @@ static void configure_smi(uint8_t smi_num, uint8_t mode) * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. * @param level SMI_LVL_LOW or SMI_LVL_HIGH */ -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) +void hudson_configure_gevent_smi(u8 gevent, u8 mode, u8 level) { - uint32_t reg32; + u32 reg32; /* GEVENT pins range from [0:23] */ if (gevent > 23) { printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); @@ -60,7 +60,7 @@ void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) }
/** Disable events from given GEVENT pin */ -void hudson_disable_gevent_smi(uint8_t gevent) +void hudson_disable_gevent_smi(u8 gevent) { /* GEVENT pins range from [0:23] */ if (gevent > 23) { diff --git a/src/southbridge/amd/pi/avalon/smihandler.c b/src/southbridge/amd/pi/avalon/smihandler.c index e762d0b..c70c856 100644 --- a/src/southbridge/amd/pi/avalon/smihandler.c +++ b/src/southbridge/amd/pi/avalon/smihandler.c @@ -26,7 +26,7 @@ enum smi_source { static void hudson_apmc_smi_handler(void) { u32 reg32; - const uint8_t cmd = inb(ACPI_SMI_CTL_PORT); + const u8 cmd = inb(ACPI_SMI_CTL_PORT);
switch (cmd) { case ACPI_SMI_CMD_ENABLE: @@ -52,7 +52,7 @@ int southbridge_io_trap_handler(int smif)
static void process_smi_sci(void) { - const uint32_t status = smi_read32(0x10); + const u32 status = smi_read32(0x10);
/* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x10, status); @@ -60,8 +60,8 @@ static void process_smi_sci(void)
static void process_gpe_smi(void) { - const uint32_t status = smi_read32(0x80); - const uint32_t gevent_mask = (1 << 24) - 1; + const u32 status = smi_read32(0x80); + const u32 gevent_mask = (1 << 24) - 1;
/* Only Bits [23:0] indicate GEVENT SMIs. */ if (status & gevent_mask) { @@ -76,7 +76,7 @@ static void process_gpe_smi(void)
static void process_smi_0x84(void) { - const uint32_t status = smi_read32(0x84); + const u32 status = smi_read32(0x84);
/* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x84, status); @@ -84,7 +84,7 @@ static void process_smi_0x84(void)
static void process_smi_0x88(void) { - const uint32_t status = smi_read32(0x88); + const u32 status = smi_read32(0x88);
if (status & SMI_0x88_ACPI_COMMAND) { /* Command received via ACPI SMI command port */ @@ -96,7 +96,7 @@ static void process_smi_0x88(void)
static void process_smi_0x8c(void) { - const uint32_t status = smi_read32(0x8c); + const u32 status = smi_read32(0x8c);
/* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x8c, status); @@ -104,7 +104,7 @@ static void process_smi_0x8c(void)
static void process_smi_0x90(void) { - const uint32_t status = smi_read32(0x90); + const u32 status = smi_read32(0x90);
/* Clear events to prevent re-entering SMI if event isn't handled */ smi_write32(0x90, status); @@ -112,7 +112,7 @@ static void process_smi_0x90(void)
void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { - const uint16_t smi_src = smi_read16(0x94); + const u16 smi_src = smi_read16(0x94);
if (smi_src & SMI_SOURCE_SCI) process_smi_sci(); @@ -130,7 +130,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
void southbridge_smi_set_eos(void) { - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + u32 reg = smi_read32(SMI_REG_SMITRIG0); reg |= SMITRG0_EOS; smi_write32(SMI_REG_SMITRIG0, reg); } diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index eba1c75..f44f786 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -254,7 +254,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; u32 lc_state, reg; - int8_t current, res = 0; + s8 current, res = 0;
while (count--) { mdelay(40); diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index 57118b8..19486cb 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -258,7 +258,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; u32 lc_state, reg, current_link_width, lane_mask; - int8_t current, res = 0; + s8 current, res = 0; u32 gfx_gpp_sb_sel; void set_pcie_dereset(void); void set_pcie_reset(void); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 82d51e6..a106a7b 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -732,7 +732,7 @@ int acpi_is_wakeup_early(void)
unsigned long get_top_of_ram(void) { - uint32_t xdata = 0; + u32 xdata = 0; int xnvram_pos = 0xfc, xi; if (!acpi_is_wakeup_early()) return 0; diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 8ebc765..2f4582d 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -93,7 +93,7 @@ static void lpc_init(device_t dev) cmos_check_update_date(); }
-void backup_top_of_ram(uint64_t ramtop) +void backup_top_of_ram(u64 ramtop) { u32 dword = (u32) ramtop; int nvram_pos = 0xfc, i; diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 2b488d9..ca22c2f 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -677,7 +677,7 @@ int acpi_is_wakeup_early(void)
unsigned long get_top_of_ram(void) { - uint32_t xdata = 0; + u32 xdata = 0; int xnvram_pos = 0xfc, xi; if (!acpi_is_wakeup_early()) return 0; diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c index 47a69af..3a5d0ec 100644 --- a/src/southbridge/broadcom/bcm21000/pcie.c +++ b/src/southbridge/broadcom/bcm21000/pcie.c @@ -29,8 +29,8 @@ static void pcie_init(struct device *dev) { /* Enable pci error detecting */ - uint32_t dword; - uint32_t msicap; + u32 dword; + u32 msicap;
printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev));
diff --git a/src/southbridge/broadcom/bcm5780/pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c index 8e01cef..82f0492 100644 --- a/src/southbridge/broadcom/bcm5780/pcie.c +++ b/src/southbridge/broadcom/bcm5780/pcie.c @@ -28,7 +28,7 @@ static void pcie_init(struct device *dev) {
/* Enable pci error detecting */ - uint32_t dword; + u32 dword;
/* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..2924280 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -23,7 +23,7 @@
static void bcm5785_enable_lpc(void) { - uint8_t byte; + u8 byte; device_t dev;
dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -44,8 +44,8 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { device_t dev; - uint32_t dword; - uint32_t dword_old; + u32 dword; + u32 dword_old;
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
@@ -135,9 +135,9 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { device_t dev; - uint32_t dword; - uint32_t dword_old; - uint8_t byte; + u32 dword; + u32 dword_old; + u8 byte;
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
@@ -160,8 +160,8 @@ static void bcm5785_enable_msg(void)
static void bcm5785_early_setup(void) { - uint8_t byte; - uint32_t dword; + u8 byte; + u32 dword; device_t dev;
//F0 diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index af79892..426f6e2 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -73,7 +73,7 @@ static void bcm5785_lpc_read_resources(device_t dev) static void bcm5785_lpc_enable_childrens_resources(device_t dev) { struct bus *link; - uint32_t reg; + u32 reg;
reg = pci_read_config8(dev, 0x44);
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c index 62eab45..84f7ba7 100644 --- a/src/southbridge/broadcom/bcm5785/sata.c +++ b/src/southbridge/broadcom/bcm5785/sata.c @@ -29,7 +29,7 @@
static void sata_init(struct device *dev) { - uint8_t byte; + u8 byte;
u32 mmio; struct resource *res; diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 3745cef..a9606d3 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -35,8 +35,8 @@
static void sb_init(device_t dev) { - uint8_t byte; - uint8_t byte_old; + u8 byte; + u8 byte_old; int nmi_option;
/* Set up NMI on errors */ @@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev) return do_smbus_recv_byte(res->base, device); }
-static int lsmbus_send_byte(device_t dev, uint8_t val) +static int lsmbus_send_byte(device_t dev, u8 val) { unsigned device; struct resource *res; @@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val) return do_smbus_send_byte(res->base, device, val); }
-static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(device_t dev, u8 address) { unsigned device; struct resource *res; @@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address) return do_smbus_read_byte(res->base, device, address); }
-static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(device_t dev, u8 address, u8 val) { unsigned device; struct resource *res; diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c index cb4a498..2c6caff 100644 --- a/src/southbridge/broadcom/bcm5785/usb.c +++ b/src/southbridge/broadcom/bcm5785/usb.c @@ -27,7 +27,7 @@
static void usb_init(struct device *dev) { - uint32_t dword; + u32 dword;
dword = pci_read_config32(dev, 0x04); dword |= (1<<2)|(1<<1)|(1<<0); diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 306e7d5..6d79cb6 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -67,7 +67,7 @@ static void pci_init(struct device *dev) static void ich_pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; - uint16_t command; + u16 command;
/* Set the subsystem vendor and device id for mainboard devices */ ops = ops_pci(dev); @@ -97,7 +97,7 @@ static void ich_pci_dev_enable_resources(struct device *dev)
static void ich_pci_bus_enable_resources(struct device *dev) { - uint16_t ctrl; + u16 ctrl; /* enable IO in command register if there is VGA card * connected with (even it does not claim IO resource) */ diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index a20232e..ecaaea9 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -229,7 +229,7 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); }
-extern uint8_t smm_relocation_start, smm_relocation_end; +extern u8 smm_relocation_start, smm_relocation_end;
static void smm_relocate(void) { diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 3f22bc7..869da7a 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -81,66 +81,66 @@ typedef struct spi_slave ich_spi_slave; static int ichspi_lock = 0;
typedef struct ich7_spi_regs { - uint16_t spis; - uint16_t spic; - uint32_t spia; - uint64_t spid[8]; - uint64_t _pad; - uint32_t bbar; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; + u16 spis; + u16 spic; + u32 spia; + u64 spid[8]; + u64 _pad; + u32 bbar; + u16 preop; + u16 optype; + u8 opmenu[8]; } __attribute__((packed)) ich7_spi_regs;
typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; + u32 bfpr; + u16 hsfs; + u16 hsfc; + u32 faddr; + u32 _reserved0; + u32 fdata[16]; + u32 frap; + u32 freg[5]; + u32 _reserved1[3]; + u32 pr[5]; + u32 _reserved2[2]; + u8 ssfs; + u8 ssfc[3]; + u16 preop; + u16 optype; + u8 opmenu[8]; + u32 bbar; + u8 _reserved3[12]; + u32 fdoc; + u32 fdod; + u8 _reserved4[8]; + u32 afc; + u32 lvscc; + u32 uvscc; + u8 _reserved5[4]; + u32 fpb; + u8 _reserved6[28]; + u32 srdl; + u32 srdc; + u32 srd; } __attribute__((packed)) ich9_spi_regs;
typedef struct ich_spi_controller { int locked; - uint32_t flmap0; - uint32_t hsfs; + u32 flmap0; + u32 hsfs;
ich9_spi_regs *ich9_spi; - uint8_t *opmenu; + u8 *opmenu; int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; + u16 *preop; + u16 *optype; + u32 *addr; + u8 *data; unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; + u8 *status; + u16 *control; + u32 *bbar; } ich_spi_controller;
static ich_spi_controller cntlr; @@ -244,22 +244,22 @@ static void writel_(u32 b, const void *addr)
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) +#define readb_(a) read8((u32)a) +#define readw_(a) read16((u32)a) +#define readl_(a) read32((u32)a) +#define writeb_(val, addr) write8((u32)addr, val) +#define writew_(val, addr) write16((u32)addr, val) +#define writel_(val, addr) write32((u32)addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
-static void write_reg(const void *value, void *dest, uint32_t size) +static void write_reg(const void *value, void *dest, u32 size) { - const uint8_t *bvalue = value; - uint8_t *bdest = dest; + const u8 *bvalue = value; + u8 *bdest = dest;
while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); + writel_(*(const u32 *)bvalue, bdest); bdest += 4; bvalue += 4; size -= 4; } while (size) { @@ -268,13 +268,13 @@ static void write_reg(const void *value, void *dest, uint32_t size) } }
-static void read_reg(const void *src, void *value, uint32_t size) +static void read_reg(const void *src, void *value, u32 size) { - const uint8_t *bsrc = src; - uint8_t *bvalue = value; + const u8 *bsrc = src; + u8 *bvalue = value;
while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); + *(u32 *)bvalue = readl_(bsrc); bsrc += 4; bvalue += 4; size -= 4; } while (size) { @@ -283,10 +283,10 @@ static void read_reg(const void *src, void *value, uint32_t size) } }
-static void ich_set_bbar(uint32_t minaddr) +static void ich_set_bbar(u32 minaddr) { - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; + const u32 bbar_mask = 0x00ffff00; + u32 ichspi_bbar;
minaddr &= bbar_mask; ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; @@ -314,12 +314,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs)
void spi_init(void) { - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ - uint8_t bios_cntl; + u8 *rcrb; /* Root Complex Register Block */ + u32 rcba; /* Root Complex Base Address */ + u8 bios_cntl; device_t dev; ich9_spi_regs *ich9_spi; - uint16_t hsfs; + u16 hsfs;
#ifdef __SMM__ dev = PCI_DEV(0, 31, 0); @@ -329,7 +329,7 @@ void spi_init(void)
pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); + rcrb = (u8 *)(rcba & 0xffffc000); ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); cntlr.ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); @@ -339,10 +339,10 @@ void spi_init(void) cntlr.menubytes = sizeof(ich9_spi->opmenu); cntlr.optype = &ich9_spi->optype; cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.data = (u8 *)ich9_spi->fdata; cntlr.databytes = sizeof(ich9_spi->fdata); cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.control = (u16 *)ich9_spi->ssfc; cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop;
@@ -381,13 +381,13 @@ void spi_release_bus(struct spi_slave *slave) }
typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; + const u8 *out; + u32 bytesout; + u8 *in; + u32 bytesin; + u8 type; + u8 opcode; + u32 offset; } spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes) @@ -438,8 +438,8 @@ static void spi_setup_type(spi_transaction *trans)
static int spi_setup_opcode(spi_transaction *trans) { - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + u16 optypes; + u8 opmenu[cntlr.menubytes];
trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -452,8 +452,8 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; } else { /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; + u8 optype; + u16 opcode_index;
/* Write Enable is handled as atomic prefix */ if (trans->opcode == SPI_OPCODE_WREN) @@ -498,9 +498,9 @@ static int spi_setup_offset(spi_transaction *trans) return 0; case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); + trans->offset = ((u32)trans->out[0] << 16) | + ((u32)trans->out[1] << 8) | + ((u32)trans->out[2] << 0); spi_use_out(trans, 3); return 1; default: @@ -551,8 +551,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { - uint16_t control; - int16_t opcode_index; + u16 control; + s16 opcode_index; int with_address; int status;
@@ -646,7 +646,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * been sent. */ while (trans.bytesout || trans.bytesin) { - uint32_t data_length; + u32 data_length;
/* SPI addresses are 24 bit only */ writel_(trans.offset & 0x00FFFFFF, cntlr.addr); @@ -697,9 +697,9 @@ int spi_xfer(struct spi_slave *slave, const void *dout, }
/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ -static void ich_hwseq_set_addr(uint32_t addr) +static void ich_hwseq_set_addr(u32 addr) { - uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; + u32 addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); }
@@ -710,8 +710,8 @@ static void ich_hwseq_set_addr(uint32_t addr) static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, unsigned int len) { - uint16_t hsfs; - uint32_t addr; + u16 hsfs; + u32 addr;
timeout /= 8; /* scale timeout duration to counter */ while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & @@ -722,7 +722,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
if (!timeout) { - uint16_t hsfc; + u16 hsfc; addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; hsfc = readw_(&cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " @@ -733,7 +733,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, }
if (hsfs & HSFS_FCERR) { - uint16_t hsfc; + u16 hsfc; addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; hsfc = readw_(&cntlr.ich9_spi->hsfc); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " @@ -750,8 +750,8 @@ static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) { u32 start, end, erase_size; int ret; - uint16_t hsfc; - uint16_t timeout = 1000 * 60; + u16 hsfc; + u16 timeout = 1000 * 60;
erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { @@ -797,10 +797,10 @@ out: return ret; }
-static void ich_read_data(uint8_t *data, int len) +static void ich_read_data(u8 *data, int len) { int i; - uint32_t temp32 = 0; + u32 temp32 = 0;
for (i = 0; i < len; i++) { if ((i % 4) == 0) @@ -813,9 +813,9 @@ static void ich_read_data(uint8_t *data, int len) static int ich_hwseq_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) { - uint16_t hsfc; - uint16_t timeout = 100 * 60; - uint8_t block_len; + u16 hsfc; + u16 timeout = 100 * 60; + u8 block_len;
if (addr + len > flash->size) { printk (BIOS_ERR, @@ -856,9 +856,9 @@ static int ich_hwseq_read(struct spi_flash *flash, * Note that using len > flash->pgm->spi.max_data_write will trash the registers * following the data registers. */ -static void ich_fill_data(const uint8_t *data, int len) +static void ich_fill_data(const u8 *data, int len) { - uint32_t temp32 = 0; + u32 temp32 = 0; int i;
if (len <= 0) @@ -868,7 +868,7 @@ static void ich_fill_data(const uint8_t *data, int len) if ((i % 4) == 0) temp32 = 0;
- temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + temp32 |= ((u32) data[i]) << ((i % 4) * 8);
if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ writel_(temp32, cntlr.data + (i - (i % 4))); @@ -881,10 +881,10 @@ static void ich_fill_data(const uint8_t *data, int len) static int ich_hwseq_write(struct spi_flash *flash, u32 addr, size_t len, const void *buf) { - uint16_t hsfc; - uint16_t timeout = 100 * 60; - uint8_t block_len; - uint32_t start = addr; + u16 hsfc; + u16 timeout = 100 * 60; + u8 block_len; + u32 start = addr;
if (addr + len > flash->size) { printk (BIOS_ERR, @@ -932,7 +932,7 @@ static int ich_hwseq_write(struct spi_flash *flash, static struct spi_flash *spi_flash_hwseq(struct spi_slave *spi) { struct spi_flash *flash = NULL; - uint32_t flcomp; + u32 flcomp;
flash = malloc(sizeof(*flash)); if (!flash) { diff --git a/src/southbridge/intel/esb6300/ehci.c b/src/southbridge/intel/esb6300/ehci.c index c103c4b..9fd0e3f 100644 --- a/src/southbridge/intel/esb6300/ehci.c +++ b/src/southbridge/intel/esb6300/ehci.c @@ -7,7 +7,7 @@
static void ehci_init(struct device *dev) { - uint32_t cmd; + u32 cmd;
printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); @@ -19,7 +19,7 @@ static void ehci_init(struct device *dev)
static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - uint8_t access_cntl; + u8 access_cntl; access_cntl = pci_read_config8(dev, 0x80); /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1); diff --git a/src/southbridge/intel/esb6300/esb6300.c b/src/southbridge/intel/esb6300/esb6300.c index 5d8f5e4..778c6a9 100644 --- a/src/southbridge/intel/esb6300/esb6300.c +++ b/src/southbridge/intel/esb6300/esb6300.c @@ -8,7 +8,7 @@ void esb6300_enable(device_t dev) { device_t lpc_dev; unsigned index = 0; - uint16_t reg_old, reg; + u16 reg_old, reg;
/* See if we are on the behind the 6300 pci bridge */ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); @@ -23,7 +23,7 @@ void esb6300_enable(device_t dev) } if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || (lpc_dev->device != PCI_DEVICE_ID_INTEL_6300ESB_LPC)) { - uint32_t id; + u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_6300ESB_LPC << 16))) { diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index b5b77ef..3b011e5 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -50,7 +50,7 @@ typedef struct southbridge_intel_esb6300_config config_t; static void set_esb6300_gpio_use_sel( device_t dev, struct resource *res, config_t *config) { - uint32_t gpio_use_sel, gpio_use_sel2; + u32 gpio_use_sel, gpio_use_sel2;
// gpio_use_sel = 0x1B003100; // gpio_use_sel2 = 0x03000000; @@ -83,7 +83,7 @@ static void set_esb6300_gpio_use_sel( static void set_esb6300_gpio_direction( device_t dev, struct resource *res, config_t *config) { - uint32_t gpio_io_sel, gpio_io_sel2; + u32 gpio_io_sel, gpio_io_sel2;
// gpio_io_sel = 0x0000ffff; // gpio_io_sel2 = 0x00000000; @@ -116,8 +116,8 @@ static void set_esb6300_gpio_direction( static void set_esb6300_gpio_level( device_t dev, struct resource *res, config_t *config) { - uint32_t gpio_lvl, gpio_lvl2; - uint32_t gpio_blink; + u32 gpio_lvl, gpio_lvl2; + u32 gpio_blink;
// gpio_lvl = 0x1b3f0000; // gpio_blink = 0x00040000; @@ -156,7 +156,7 @@ static void set_esb6300_gpio_level( static void set_esb6300_gpio_inv( device_t dev, struct resource *res, config_t *config) { - uint32_t gpio_inv; + u32 gpio_inv;
gpio_inv = 0x00003100; #if 0 @@ -230,8 +230,8 @@ static void esb6300_gpio_init(device_t dev)
static void lpc_init(struct device *dev) { - uint8_t byte; - uint32_t value; + u8 byte; + u32 value; int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* sata settings */ @@ -337,7 +337,7 @@ static void esb6300_lpc_read_resources(device_t dev)
static void esb6300_lpc_enable_resources(device_t dev) { - uint8_t acpi_cntl, gpio_cntl; + u8 acpi_cntl, gpio_cntl;
/* Enable the normal pci resources */ pci_dev_enable_resources(dev); diff --git a/src/southbridge/intel/esb6300/pci.c b/src/southbridge/intel/esb6300/pci.c index 991cd7b..96561f2 100644 --- a/src/southbridge/intel/esb6300/pci.c +++ b/src/southbridge/intel/esb6300/pci.c @@ -8,7 +8,7 @@ static void pci_init(struct device *dev) {
- uint16_t word; + u16 word;
/* Clear system errors */ word = pci_read_config16(dev, 0x06); diff --git a/src/southbridge/intel/esb6300/pic.c b/src/southbridge/intel/esb6300/pic.c index e3fc2b2..fecdb51 100644 --- a/src/southbridge/intel/esb6300/pic.c +++ b/src/southbridge/intel/esb6300/pic.c @@ -12,7 +12,7 @@ static void pic_init(struct device *dev) {
- uint16_t word; + u16 word;
/* Clear system errors */ word = pci_read_config16(dev, 0x06); diff --git a/src/southbridge/intel/esb6300/uhci.c b/src/southbridge/intel/esb6300/uhci.c index 0b65b01..670415c 100644 --- a/src/southbridge/intel/esb6300/uhci.c +++ b/src/southbridge/intel/esb6300/uhci.c @@ -7,7 +7,7 @@
static void uhci_init(struct device *dev) { - uint32_t cmd; + u32 cmd;
#if 1 printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index 827b897..98e47b3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -232,7 +232,7 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); }
-extern uint8_t smm_relocation_start, smm_relocation_end; +extern u8 smm_relocation_start, smm_relocation_end;
static void smm_relocate(void) { diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 844f4b8..c448fb2 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -52,9 +52,9 @@ static void rangeley_setup_bars(void)
static void reset_rtc(void) { - uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & + u32 pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0; - uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1); + u32 gen_pmcon1 = read32(pbase + GEN_PMCON1); int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) { diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 9644067..0391d79 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -120,13 +120,13 @@ static void write_pci_config_irqs(void) { device_t irq_dev; device_t targ_dev; - uint8_t int_line = 0; - uint8_t original_int_pin = 0; - uint8_t new_int_pin = 0; - uint16_t current_bdf = 0; - uint16_t parent_bdf = 0; - uint8_t pirq = 0; - uint8_t device_num = 0; + u8 int_line = 0; + u8 original_int_pin = 0; + u8 new_int_pin = 0; + u16 current_bdf = 0; + u16 parent_bdf = 0; + u8 pirq = 0; + u8 device_num = 0; const struct rangeley_irq_route *ir = &global_rangeley_irq_route;
if (ir == NULL) { diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 6c5751e..921a8be 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -41,8 +41,8 @@
void main(FSP_INFO_HEADER *fsp_info_header) { - uint32_t fd_mask = 0; - uint32_t func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS; + u32 fd_mask = 0; + u32 func_dis = DEFAULT_PBASE + PBASE_FUNC_DIS;
/* * Do not use the Serial Console before it is setup. diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index ee22019..d6782b6 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -70,96 +70,96 @@ typedef struct spi_slave ich_spi_slave; static int ichspi_lock = 0;
typedef struct ich7_spi_regs { - uint16_t spis; - uint16_t spic; - uint32_t spia; - uint64_t spid[8]; - uint64_t _pad; - uint32_t bbar; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; + u16 spis; + u16 spic; + u32 spia; + u64 spid[8]; + u64 _pad; + u32 bbar; + u16 preop; + u16 optype; + u8 opmenu[8]; } __attribute__((packed)) ich7_spi_regs;
typedef struct ich9_spi_regs { - uint32_t bfpr; // 0 - uint16_t hsfs; // 4 - uint16_t hsfc; // 6 - uint32_t faddr; // 8 - uint32_t _reserved0; // 0xC - uint32_t fdata[16]; // 0x10 - uint32_t frap; // 0x50 - uint32_t freg[5]; // 0x54 - uint32_t _reserved1[3]; // 0x67 - uint32_t pr[5]; // 0x74 - uint32_t _reserved2[2]; // 0x88 - uint8_t ssfs; // 0x90 - uint8_t ssfc[3]; // 0x91 - uint16_t preop; // 0x94 - uint16_t optype; // 0x96 - uint8_t opmenu[8]; // 0x98 - uint32_t bbar; // 0xB0 - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; + u32 bfpr; // 0 + u16 hsfs; // 4 + u16 hsfc; // 6 + u32 faddr; // 8 + u32 _reserved0; // 0xC + u32 fdata[16]; // 0x10 + u32 frap; // 0x50 + u32 freg[5]; // 0x54 + u32 _reserved1[3]; // 0x67 + u32 pr[5]; // 0x74 + u32 _reserved2[2]; // 0x88 + u8 ssfs; // 0x90 + u8 ssfc[3]; // 0x91 + u16 preop; // 0x94 + u16 optype; // 0x96 + u8 opmenu[8]; // 0x98 + u32 bbar; // 0xB0 + u8 _reserved3[12]; + u32 fdoc; + u32 fdod; + u8 _reserved4[8]; + u32 afc; + u32 lvscc; + u32 uvscc; + u8 _reserved5[4]; + u32 fpb; + u8 _reserved6[28]; + u32 srdl; + u32 srdc; + u32 srd; } __attribute__((packed)) ich9_spi_regs;
typedef struct ich10_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t fracc; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint8_t _reserved3[16]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[36]; - uint32_t scs; - uint32_t bcr; - uint32_t tcgc; + u32 bfpr; + u16 hsfs; + u16 hsfc; + u32 faddr; + u32 _reserved0; + u32 fdata[16]; + u32 fracc; + u32 freg[5]; + u32 _reserved1[3]; + u32 pr[5]; + u32 _reserved2[2]; + u8 ssfs; + u8 ssfc[3]; + u16 preop; + u16 optype; + u8 opmenu[8]; + u8 _reserved3[16]; + u32 fdoc; + u32 fdod; + u8 _reserved4[8]; + u32 afc; + u32 lvscc; + u32 uvscc; + u8 _reserved5[4]; + u32 fpb; + u8 _reserved6[36]; + u32 scs; + u32 bcr; + u32 tcgc; } __attribute__((packed)) ich10_spi_regs;
typedef struct ich_spi_controller { int locked;
- uint8_t *opmenu; + u8 *opmenu; int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; + u16 *preop; + u16 *optype; + u32 *addr; + u8 *data; unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; - uint8_t *bcr; + u8 *status; + u16 *control; + u32 *bbar; + u8 *bcr; } ich_spi_controller;
static ich_spi_controller cntlr; @@ -276,22 +276,22 @@ static void writel_(u32 b, const void *addr)
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
-#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) +#define readb_(a) read8((u32)a) +#define readw_(a) read16((u32)a) +#define readl_(a) read32((u32)a) +#define writeb_(val, addr) write8((u32)addr, val) +#define writew_(val, addr) write16((u32)addr, val) +#define writel_(val, addr) write32((u32)addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
-static void write_reg(const void *value, void *dest, uint32_t size) +static void write_reg(const void *value, void *dest, u32 size) { - const uint8_t *bvalue = value; - uint8_t *bdest = dest; + const u8 *bvalue = value; + u8 *bdest = dest;
while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); + writel_(*(const u32 *)bvalue, bdest); bdest += 4; bvalue += 4; size -= 4; } while (size) { @@ -300,13 +300,13 @@ static void write_reg(const void *value, void *dest, uint32_t size) } }
-static void read_reg(const void *src, void *value, uint32_t size) +static void read_reg(const void *src, void *value, u32 size) { - const uint8_t *bsrc = src; - uint8_t *bvalue = value; + const u8 *bsrc = src; + u8 *bvalue = value;
while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); + *(u32 *)bvalue = readl_(bsrc); bsrc += 4; bvalue += 4; size -= 4; } while (size) { @@ -315,10 +315,10 @@ static void read_reg(const void *src, void *value, uint32_t size) } }
-static void ich_set_bbar(uint32_t minaddr) +static void ich_set_bbar(u32 minaddr) { - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; + const u32 bbar_mask = 0x00ffff00; + u32 ichspi_bbar;
if (cntlr.bbar == NULL) return; @@ -350,7 +350,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) * * Return the ICH version if there is a match, or zero otherwise. */ -static inline int get_ich_version(uint16_t device_id) +static inline int get_ich_version(u16 device_id) {
if ((device_id >= PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MIN && @@ -363,10 +363,10 @@ static inline int get_ich_version(uint16_t device_id) void spi_init(void) { int ich_version = 0; - uint8_t bios_cntl; + u8 bios_cntl; device_t dev; - uint32_t ids; - uint16_t vendor_id, device_id; + u32 ids; + u16 vendor_id, device_id;
#ifdef __SMM__ dev = PCI_DEV(0, 31, 0); @@ -392,11 +392,11 @@ void spi_init(void) switch (ich_version) { case 10: { - uint8_t *spibase; /* SPI Base Address */ - uint32_t sbase; /* SPI Base Address Register */ + u8 *spibase; /* SPI Base Address */ + u32 sbase; /* SPI Base Address Register */ pci_read_config_dword(dev, 0x54, &sbase); /* Bits 31-9 are the base address, 8-4 are reserved, 3-0 are used. */ - spibase = (uint8_t *)(sbase & 0xffffff00); + spibase = (u8 *)(sbase & 0xffffff00); ich10_spi_regs *ich10_spi = (ich10_spi_regs *)(spibase); ichspi_lock = readw_(&ich10_spi->hsfs) & HSFS_FLOCKDN; @@ -404,13 +404,13 @@ void spi_init(void) cntlr.menubytes = sizeof(ich10_spi->opmenu); cntlr.optype = &ich10_spi->optype; cntlr.addr = &ich10_spi->faddr; - cntlr.data = (uint8_t *)ich10_spi->fdata; + cntlr.data = (u8 *)ich10_spi->fdata; cntlr.databytes = sizeof(ich10_spi->fdata); cntlr.status = &ich10_spi->ssfs; - cntlr.control = (uint16_t *)ich10_spi->ssfc; + cntlr.control = (u16 *)ich10_spi->ssfc; cntlr.bbar = NULL; cntlr.preop = &ich10_spi->preop; - cntlr.bcr = (uint8_t *)&ich10_spi->bcr; + cntlr.bcr = (u8 *)&ich10_spi->bcr; break; } default: @@ -448,13 +448,13 @@ void spi_release_bus(struct spi_slave *slave) }
typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; + const u8 *out; + u32 bytesout; + u8 *in; + u32 bytesin; + u8 type; + u8 opcode; + u32 offset; } spi_transaction;
static inline void spi_use_out(spi_transaction *trans, unsigned bytes) @@ -505,8 +505,8 @@ static void spi_setup_type(spi_transaction *trans)
static int spi_setup_opcode(spi_transaction *trans) { - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + u16 optypes; + u8 opmenu[cntlr.menubytes];
trans->opcode = trans->out[0]; spi_use_out(trans, 1); @@ -519,8 +519,8 @@ static int spi_setup_opcode(spi_transaction *trans) return 0; } else { /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; + u8 optype; + u16 opcode_index;
/* Write Enable is handled as atomic prefix */ if (trans->opcode == SPI_OPCODE_WREN) @@ -565,9 +565,9 @@ static int spi_setup_offset(spi_transaction *trans) return 0; case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); + trans->offset = ((u32)trans->out[0] << 16) | + ((u32)trans->out[1] << 8) | + ((u32)trans->out[2] << 0); spi_use_out(trans, 3); return 1; default: @@ -611,8 +611,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { - uint16_t control; - int16_t opcode_index; + u16 control; + s16 opcode_index; int with_address; int status;
@@ -705,7 +705,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * been sent. */ while (trans.bytesout || trans.bytesin) { - uint32_t data_length; + u32 data_length;
/* SPI addresses are 24 bit only */ writel_(trans.offset & 0x00FFFFFF, cntlr.addr); diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 11519c1..72eb773 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -142,7 +142,7 @@ static void i82801ax_pirq_init(device_t dev)
static void i82801ax_power_options(device_t dev) { - uint8_t byte; + u8 byte; int pwr_on = -1; int nmi_option;
@@ -178,8 +178,8 @@ static void gpio_init(device_t dev)
static void i82801ax_rtc_init(struct device *dev) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32; int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3); @@ -196,9 +196,9 @@ static void i82801ax_rtc_init(struct device *dev) pci_write_config8(dev, RTC_CONF, 0x04); }
-static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask) +static void i82801ax_lpc_route_dma(struct device *dev, u8 mask) { - uint16_t reg16; + u16 reg16; int i;
reg16 = pci_read_config16(dev, PCI_DMA_CFG); diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 278d65c..8ea751c 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -123,7 +123,7 @@ static void i82801bx_enable_serial_irqs(struct device *dev) /* TODO: Explain/#define the real meaning of these magic numbers. */ }
-static void i82801bx_pirq_init(device_t dev, uint16_t ich_model) +static void i82801bx_pirq_init(device_t dev, u16 ich_model) { u8 reg8; config_t *config = dev->chip_info; @@ -156,7 +156,7 @@ static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)
static void i82801bx_power_options(device_t dev) { - uint8_t byte; + u8 byte; int pwr_on = -1; int nmi_option;
@@ -193,8 +193,8 @@ static void gpio_init(device_t dev)
static void i82801bx_rtc_init(struct device *dev) { - uint8_t reg8; - uint32_t reg32; + u8 reg8; + u32 reg32; int rtc_failed;
reg8 = pci_read_config8(dev, GEN_PMCON_3); @@ -211,9 +211,9 @@ static void i82801bx_rtc_init(struct device *dev) pci_write_config8(dev, RTC_CONF, 0x04); }
-static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) +static void i82801bx_lpc_route_dma(struct device *dev, u8 mask) { - uint16_t reg16; + u16 reg16; int i;
reg16 = pci_read_config16(dev, PCI_DMA_CFG); @@ -226,7 +226,7 @@ static void i82801bx_lpc_route_dma(struct device *dev, uint8_t mask) pci_write_config16(dev, PCI_DMA_CFG, reg16); }
-static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) +static void i82801bx_lpc_decode_en(device_t dev, u16 ich_model) { /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. @@ -239,7 +239,7 @@ static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model)
static void lpc_init(struct device *dev) { - uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); + u16 ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
/* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82801cx/i82801cx.c b/src/southbridge/intel/i82801cx/i82801cx.c index 685c931..978eda3 100644 --- a/src/southbridge/intel/i82801cx/i82801cx.c +++ b/src/southbridge/intel/i82801cx/i82801cx.c @@ -8,8 +8,8 @@ void i82801cx_enable(device_t dev) { unsigned int index = 0; - uint8_t bHasDisableBit = 0; - uint16_t cur_disable_mask, new_disable_mask; + u8 bHasDisableBit = 0; + u16 cur_disable_mask, new_disable_mask;
// all 82801ca devices are in bus 0 unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc diff --git a/src/southbridge/intel/i82801cx/ide.c b/src/southbridge/intel/i82801cx/ide.c index 74c442c..415ea73 100644 --- a/src/southbridge/intel/i82801cx/ide.c +++ b/src/southbridge/intel/i82801cx/ide.c @@ -9,7 +9,7 @@ static void ide_init(struct device *dev) { /* Enable ide devices so the linux ide driver will work */ - uint16_t ideTimingConfig; + u16 ideTimingConfig; int enable_primary = 1; int enable_secondary = 1;
diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index f6c33b7..142428e 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -65,9 +65,9 @@ static void i82801cx_enable_serial_irqs( struct device *dev) * (bit = 0) or LPC DMA (bit = 1). The LSb controls channel 0. * Channel 4 is not used (reserved). */ -static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) +static void i82801cx_lpc_route_dma( struct device *dev, u8 mask) { - uint16_t dmaConfig; + u16 dmaConfig; int channelIndex;
dmaConfig = pci_read_config16(dev, PCI_DMA_CFG); @@ -82,10 +82,10 @@ static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask)
static void i82801cx_rtc_init(struct device *dev) { - uint32_t dword; + u32 dword; int rtc_failed; int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3); + u8 pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = pmcon3 & RTC_BATTERY_DEAD; if (rtc_failed) { @@ -152,7 +152,7 @@ static void i82801cx_1f0_misc(struct device *dev)
static void lpc_init(struct device *dev) { - uint8_t byte; + u8 byte; int pwr_on=-1; int nmi_option;
diff --git a/src/southbridge/intel/i82801cx/pci.c b/src/southbridge/intel/i82801cx/pci.c index 1ebe8c7..1042fda 100644 --- a/src/southbridge/intel/i82801cx/pci.c +++ b/src/southbridge/intel/i82801cx/pci.c @@ -9,7 +9,7 @@ static void pci_init(struct device *dev) { // NOTE: the original (v1) 'CA code set these in the bridge register (0x3E-3F) /* Enable pci error detecting */ - uint32_t dword = pci_read_config32(dev, PCI_COMMAND); + u32 dword = pci_read_config32(dev, PCI_COMMAND); dword |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); pci_write_config32(dev, PCI_COMMAND, dword); } diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c index 05f7487..a2d2c3b 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.c +++ b/src/southbridge/intel/i82801dx/i82801dx.c @@ -27,8 +27,8 @@ void i82801dx_enable(device_t dev) { unsigned int index = 0; - uint8_t bHasDisableBit = 0; - uint16_t cur_disable_mask, new_disable_mask; + u8 bHasDisableBit = 0; + u16 cur_disable_mask, new_disable_mask;
// all 82801dbm devices are in bus 0 unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc diff --git a/src/southbridge/intel/i82801dx/ide.c b/src/southbridge/intel/i82801dx/ide.c index 82592fc..9df378e 100644 --- a/src/southbridge/intel/i82801dx/ide.c +++ b/src/southbridge/intel/i82801dx/ide.c @@ -33,7 +33,7 @@ static void ide_init(struct device *dev) config_t *config = dev->chip_info;
/* Enable IDE devices so the Linux IDE driver will work. */ - uint16_t ideTimingConfig; + u16 ideTimingConfig;
ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI); ideTimingConfig &= ~IDE_DECODE_ENABLE; diff --git a/src/southbridge/intel/i82801dx/pci.c b/src/southbridge/intel/i82801dx/pci.c index 610ec1e..f32e403 100644 --- a/src/southbridge/intel/i82801dx/pci.c +++ b/src/southbridge/intel/i82801dx/pci.c @@ -27,7 +27,7 @@ static void pci_init(struct device *dev) { /* Enable pci error detecting */ - uint32_t dword; + u32 dword; /* System error enable */ dword = pci_read_config32(dev, 0x04); dword |= (1 << 8); /* SERR# Enable */ diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index d2e3e25..5978cf1 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -236,7 +236,7 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); }
-extern uint8_t smm_relocation_start, smm_relocation_end; +extern u8 smm_relocation_start, smm_relocation_end;
static void smm_relocate(void) { diff --git a/src/southbridge/intel/i82801ex/ehci.c b/src/southbridge/intel/i82801ex/ehci.c index 28164c5..d370aea 100644 --- a/src/southbridge/intel/i82801ex/ehci.c +++ b/src/southbridge/intel/i82801ex/ehci.c @@ -8,7 +8,7 @@
static void ehci_init(struct device *dev) { - uint32_t cmd; + u32 cmd;
printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); @@ -20,7 +20,7 @@ static void ehci_init(struct device *dev)
static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - uint8_t access_cntl; + u8 access_cntl; access_cntl = pci_read_config8(dev, 0x80); /* Enable writes to protected registers */ pci_write_config8(dev, 0x80, access_cntl | 1); diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index fc41645..3c81cb2 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -8,7 +8,7 @@ void i82801ex_enable(device_t dev) { device_t lpc_dev; unsigned index = 0; - uint16_t reg_old, reg; + u16 reg_old, reg;
/* See if we are behind the i82801ex pci bridge */ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); @@ -23,7 +23,7 @@ void i82801ex_enable(device_t dev) } if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_LPC)) { - uint32_t id; + u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_LPC << 16))) { diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 1823e65..5a2069a 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -87,7 +87,7 @@ typedef struct southbridge_intel_i82801ex_config config_t; static void set_i82801ex_gpio_use_sel( device_t dev, struct resource *res, config_t *config) { - uint32_t gpio_use_sel, gpio_use_sel2; + u32 gpio_use_sel, gpio_use_sel2; int i;
gpio_use_sel = 0x1A003180; @@ -116,7 +116,7 @@ static void set_i82801ex_gpio_use_sel( static void set_i82801ex_gpio_direction( device_t dev, struct resource *res, config_t *config) { - uint32_t gpio_io_sel, gpio_io_sel2; + u32 gpio_io_sel, gpio_io_sel2; int i;
gpio_io_sel = 0x0000ffff; @@ -145,8 +145,8 @@ static void set_i82801ex_gpio_direction( static void set_i82801ex_gpio_level( device_t dev, struct resource *res, config_t *config) { - uint32_t gpio_lvl, gpio_lvl2; - uint32_t gpio_blink; + u32 gpio_lvl, gpio_lvl2; + u32 gpio_blink; int i;
gpio_lvl = 0x1b3f0000; @@ -180,7 +180,7 @@ static void set_i82801ex_gpio_level( static void set_i82801ex_gpio_inv( device_t dev, struct resource *res, config_t *config) { - uint32_t gpio_inv; + u32 gpio_inv; int i;
gpio_inv = 0x00000000; @@ -253,8 +253,8 @@ static void enable_hpet(struct device *dev) { const unsigned long hpet_address = 0xfed00000;
- uint32_t dword; - uint32_t code = (0 & 0x3); + u32 dword; + u32 code = (0 & 0x3);
dword = pci_read_config32(dev, GEN_CNTL); dword |= (1 << 17); /* enable hpet */ @@ -275,7 +275,7 @@ static void enable_hpet(struct device *dev)
static void lpc_init(struct device *dev) { - uint8_t byte; + u8 byte; int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
i82801ex_general_cntl(dev); diff --git a/src/southbridge/intel/i82801ex/pci.c b/src/southbridge/intel/i82801ex/pci.c index f1c8183..c429082 100644 --- a/src/southbridge/intel/i82801ex/pci.c +++ b/src/southbridge/intel/i82801ex/pci.c @@ -7,7 +7,7 @@
static void pci_init(struct device *dev) { - uint16_t word; + u16 word;
/* Clear system errors */ word = pci_read_config16(dev, 0x06); diff --git a/src/southbridge/intel/i82801ex/uhci.c b/src/southbridge/intel/i82801ex/uhci.c index c9cf82e..a43f4be 100644 --- a/src/southbridge/intel/i82801ex/uhci.c +++ b/src/southbridge/intel/i82801ex/uhci.c @@ -7,7 +7,7 @@
static void uhci_init(struct device *dev) { - uint32_t cmd; + u32 cmd;
#if 1 printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 0f372e7..41cbad3 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -66,7 +66,7 @@ static void pci_init(struct device *dev) static void ich_pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; - uint16_t command; + u16 command;
/* Set the subsystem vendor and device id for mainboard devices */ ops = ops_pci(dev); @@ -94,7 +94,7 @@ static void ich_pci_dev_enable_resources(struct device *dev)
static void ich_pci_bus_enable_resources(struct device *dev) { - uint16_t ctrl; + u16 ctrl; /* enable IO in command register if there is VGA card * connected with (even it does not claim IO resource) */ diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 134c232..7abf2b3 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -236,7 +236,7 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); }
-extern uint8_t smm_relocation_start, smm_relocation_end; +extern u8 smm_relocation_start, smm_relocation_end;
static void smm_relocate(void) { diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index de9931c..f7f0dcf 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -240,7 +240,7 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); }
-extern uint8_t smm_relocation_start, smm_relocation_end; +extern u8 smm_relocation_start, smm_relocation_end;
static void smm_relocate(void) { diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 6a0f0d2..d918466 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -12,7 +12,7 @@ static int num_p64h2_ioapics = 0; static void p64h2_ioapic_enable(device_t dev) { /* We have to enable MEM and Bus Master for IOAPIC */ - uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + u16 command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, command); @@ -29,11 +29,11 @@ static void p64h2_ioapic_enable(device_t dev) */ static void p64h2_ioapic_init(device_t dev) { - uint32_t memoryBase; + u32 memoryBase; int apic_index, apic_id;
- volatile uint32_t* pIndexRegister; /* io apic io memory space command address */ - volatile uint32_t* pWindowRegister; /* io apic io memory space data address */ + volatile u32* pIndexRegister; /* io apic io memory space command address */ + volatile u32* pWindowRegister; /* io apic io memory space data address */
apic_index = num_p64h2_ioapics; num_p64h2_ioapics++; @@ -59,8 +59,8 @@ static void p64h2_ioapic_init(device_t dev) // NOTE: this address was assigned during enumeration of the bus
memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - pIndexRegister = (volatile uint32_t*) memoryBase; - pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); + pIndexRegister = (volatile u32*) memoryBase; + pWindowRegister = (volatile u32*)(memoryBase + 0x10);
printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n", apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c index 71d2c53..7f5cb0f 100644 --- a/src/southbridge/intel/i82870/pci_parity.c +++ b/src/southbridge/intel/i82870/pci_parity.c @@ -5,7 +5,7 @@
void p64h2_pci_parity_enable(void) { - uint8_t reg; + u8 reg;
/* 2SERREN - SERR enable for PCI bridge secondary device */ /* 2PEREN - Parity error for PCI bridge secondary device */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2ce9072..8d1361a 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -231,7 +231,7 @@ static void smi_set_eos(void) outb(reg8, pmbase + SMI_EN); }
-extern uint8_t smm_relocation_start, smm_relocation_end; +extern u8 smm_relocation_start, smm_relocation_end;
static void smm_relocate(void) { diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c index 306e7d5..6d79cb6 100644 --- a/src/southbridge/intel/lynxpoint/pci.c +++ b/src/southbridge/intel/lynxpoint/pci.c @@ -67,7 +67,7 @@ static void pci_init(struct device *dev) static void ich_pci_dev_enable_resources(struct device *dev) { const struct pci_operations *ops; - uint16_t command; + u16 command;
/* Set the subsystem vendor and device id for mainboard devices */ ops = ops_pci(dev); @@ -97,7 +97,7 @@ static void ich_pci_dev_enable_resources(struct device *dev)
static void ich_pci_bus_enable_resources(struct device *dev) { - uint16_t ctrl; + u16 ctrl; /* enable IO in command register if there is VGA card * connected with (even it does not claim IO resource) */ diff --git a/src/southbridge/intel/sch/smi.c b/src/southbridge/intel/sch/smi.c index 08733a7..91a9206 100644 --- a/src/southbridge/intel/sch/smi.c +++ b/src/southbridge/intel/sch/smi.c @@ -240,7 +240,7 @@ static void smi_set_eos(void) #endif }
-extern uint8_t smm_relocation_start, smm_relocation_end; +extern u8 smm_relocation_start, smm_relocation_end;
static void smm_relocate(void) { diff --git a/src/southbridge/rdc/r8610/bootblock.c b/src/southbridge/rdc/r8610/bootblock.c index 2e5e360..1328414 100644 --- a/src/southbridge/rdc/r8610/bootblock.c +++ b/src/southbridge/rdc/r8610/bootblock.c @@ -21,7 +21,7 @@ #include <device/pci_def.h>
static void bootblock_southbridge_init(void) { - uint32_t tmp; + u32 tmp; tmp = pci_read_config32(PCI_DEV(0,7,0), 0x40); /* decode all flash ranges */ pci_write_config32(PCI_DEV(0,7,0), 0x40, tmp | 0x07ff0000); diff --git a/src/southbridge/sis/sis966/early_setup_car.c b/src/southbridge/sis/sis966/early_setup_car.c index cf4315c..a2f44d8 100644 --- a/src/southbridge/sis/sis966/early_setup_car.c +++ b/src/southbridge/sis/sis966/early_setup_car.c @@ -23,9 +23,9 @@
void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { - uint32_t tgio_ctrl; - uint32_t pll_ctrl; - uint32_t dword; + u32 tgio_ctrl; + u32 pll_ctrl; + u32 dword; int i; device_t dev; dev = PCI_DEV(busnx, devnx+1, 1); diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 06130db..0923b1d 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -191,7 +191,7 @@ static inline int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, u
-static const uint8_t SiS_LPC_init[34][3]={ +static const u8 SiS_LPC_init[34][3]={ {0x04, 0xF8, 0x07}, //Reg 0x04 {0x45, 0x00, 0x00}, //Reg 0x45 //Enable Rom Flash {0x46, 0x00, 0x3D}, //Reg 0x46 @@ -228,7 +228,7 @@ static const uint8_t SiS_LPC_init[34][3]={ {0x00, 0x00, 0x00} //End of table };
-static const uint8_t SiS_NBPCIE_init[43][3]={ +static const u8 SiS_NBPCIE_init[43][3]={ {0x3D, 0x00, 0x00}, //Reg 0x3D {0x1C, 0xFE, 0x01}, //Reg 0x1C {0x1D, 0xFE, 0x01}, //Reg 0x1D @@ -274,7 +274,7 @@ static const uint8_t SiS_NBPCIE_init[43][3]={ {0x00, 0x00, 0x00} //End of table };
-static const uint8_t SiS_ACPI_init[10][3]={ +static const u8 SiS_ACPI_init[10][3]={ {0x1B, 0xBF, 0x40}, //Reg 0x1B {0x84, 0x00, 0x0E}, //Reg 0x84 {0x85, 0x00, 0x29}, //Reg 0x85 @@ -287,7 +287,7 @@ static const uint8_t SiS_ACPI_init[10][3]={ {0x00, 0x00, 0x00} //End of table };
-static const uint8_t SiS_SBPCIE_init[13][3]={ +static const u8 SiS_SBPCIE_init[13][3]={ {0x48, 0x00 ,0x07}, //Reg 0x48 {0x49, 0x00 ,0x06}, //Reg 0x49 {0x4A, 0x00 ,0x0C}, //Reg 0x4A @@ -303,7 +303,7 @@ static const uint8_t SiS_SBPCIE_init[13][3]={ {0x00, 0x00, 0x00} //End of table };
-static const uint8_t SiS_NB_init[56][3]={ +static const u8 SiS_NB_init[56][3]={ {0x04, 0x00 ,0x07}, //Reg 0x04 {0x05, 0x00 ,0x00}, //Reg 0x05 // alex {0x0D, 0x00 ,0x20}, //Reg 0x0D @@ -362,7 +362,7 @@ static const uint8_t SiS_NB_init[56][3]={ {0x00, 0x00, 0x00} //End of table };
-static const uint8_t SiS_NBAGP_init[34][3]={ +static const u8 SiS_NBAGP_init[34][3]={ {0xCF, 0xDF, 0x00}, //HT issue {0x06, 0xDF, 0x20}, {0x1E, 0xDF, 0x20}, @@ -399,7 +399,7 @@ static const uint8_t SiS_NBAGP_init[34][3]={ {0x00, 0x00, 0x00} //End of table };
-static const uint8_t SiS_ACPI_2_init[56][3]={ +static const u8 SiS_ACPI_2_init[56][3]={ {0x00, 0x00, 0xFF}, //Reg 0x00 {0x01, 0x00, 0xFF}, //Reg 0x01 {0x02, 0x00, 0x00}, //Reg 0x02 @@ -458,7 +458,7 @@ static const uint8_t SiS_ACPI_2_init[56][3]={ {0x00, 0x00, 0x00} //End of table };
-static const uint8_t SiS_SiS1183_init[44][3]={ +static const u8 SiS_SiS1183_init[44][3]={ {0x04, 0x00, 0x05}, {0x09, 0x00, 0x05}, {0x2C, 0x00, 0x39}, @@ -512,7 +512,7 @@ static const uint8_t SiS_SiS1183_init[44][3]={ => 04h : 128MBytes => Others: Reserved */ -static void Init_Share_Memory(uint8_t ShareSize) +static void Init_Share_Memory(u8 ShareSize) { device_t dev;
@@ -528,10 +528,10 @@ static void Init_Share_Memory(uint8_t ShareSize) => 04h : 512MBytes => Others: Reserved */ -static void Init_Aper_Size(uint8_t AperSize) +static void Init_Aper_Size(u8 AperSize) { device_t dev; - uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00}; + u16 SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0); pci_write_config8(dev, 0x90, AperSize << 1); @@ -543,9 +543,9 @@ static void Init_Aper_Size(uint8_t AperSize) static void sis_init_stage1(void) { device_t dev; - uint8_t temp8; + u8 temp8; int i; - uint8_t GUI_En; + u8 GUI_En;
// SiS_Chipset_Initialization // ========================== NB ============================= @@ -607,8 +607,8 @@ static void sis_init_stage2(void) device_t dev; msr_t msr; int i; - uint8_t temp8; - uint16_t temp16; + u8 temp8; + u16 temp16;
// ========================== NB_AGP ============================= @@ -717,7 +717,7 @@ static void sis_init_stage2(void) static void enable_smbus(void) { device_t dev; - uint8_t temp8; + u8 temp8; printk(BIOS_DEBUG, "enable_smbus -------->\n");
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index ddfcead..f819766 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -32,7 +32,7 @@ #include "sis966.h" #include "chip.h"
-uint8_t SiS_SiS5513_init[49][3]={ +u8 SiS_SiS5513_init[49][3]={ {0x04, 0xFF, 0x05}, {0x0D, 0xFF, 0x80}, {0x2C, 0xFF, 0x39}, @@ -93,9 +93,9 @@ static void ide_init(struct device *dev) { struct southbridge_sis_sis966_config *conf; /* Enable ide devices so the linux ide driver will work */ - uint32_t dword; - uint16_t word; - uint8_t byte; + u32 dword; + u16 word; + u8 byte; conf = dev->chip_info;
@@ -105,7 +105,7 @@ print_debug("IDE_INIT:---------->\n");
//-------------- enable IDE (SiS5513) ------------------------- { - uint8_t temp8; + u8 temp8; int i=0; while(SiS_SiS5513_init[i][0] != 0) { diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index a61883b..7e43fe6 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -58,8 +58,8 @@
static void lpc_common_init(device_t dev) { - uint8_t byte; - uint32_t ioapic_base; + u8 byte; + u32 ioapic_base;
/* IO APIC initialization */ byte = pci_read_config8(dev, 0x74); @@ -79,7 +79,7 @@ static void lpc_slave_init(device_t dev)
static void lpc_usb_legacy_init(device_t dev) { - uint16_t acpi_base; + u16 acpi_base;
acpi_base = (pci_read_config8(dev,0x75) << 8);
@@ -89,8 +89,8 @@ static void lpc_usb_legacy_init(device_t dev)
static void lpc_init(device_t dev) { - uint8_t byte; - uint8_t byte_old; + u8 byte; + u8 byte_old; int on; int nmi_option;
@@ -117,8 +117,8 @@ static void lpc_init(device_t dev) on = SLOW_CPU_OFF; get_option(&on, "slow_cpu"); if(on) { - uint16_t pm10_bar; - uint32_t dword; + u16 pm10_bar; + u32 dword; pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); @@ -190,7 +190,7 @@ static void sis966_lpc_read_resources(device_t dev) static void sis966_lpc_enable_childrens_resources(device_t dev) { struct bus *link; - uint32_t reg, reg_var[4]; + u32 reg, reg_var[4]; int i; int var_num = 0;
diff --git a/src/southbridge/sis/sis966/pcie.c b/src/southbridge/sis/sis966/pcie.c index a0b696e..0982577 100644 --- a/src/southbridge/sis/sis966/pcie.c +++ b/src/southbridge/sis/sis966/pcie.c @@ -34,7 +34,7 @@ static void pcie_init(struct device *dev) {
/* Enable pci error detecting */ - uint32_t dword; + u32 dword;
/* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 3f8c28f..807410d 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -32,7 +32,7 @@ #include "sis966.h" #include <arch/io.h>
-uint8_t SiS_SiS1183_init[68][3]={ +u8 SiS_SiS1183_init[68][3]={ {0x04, 0x00, 0x05}, {0x09, 0x00, 0x05}, {0x2C, 0x00, 0x39}, @@ -120,7 +120,7 @@ static void sata_init(struct device *dev)
//-------------- enable IDE (SiS1183) ------------------------- { - uint8_t temp8; + u8 temp8; int i=0; while(SiS_SiS1183_init[i][0] != 0) { @@ -134,8 +134,8 @@ static void sata_init(struct device *dev) //-----------------------------------------------------------
{ -uint32_t i,j; -uint32_t temp32; +u32 i,j; +u32 temp32;
for (i=0;i<10;i++){ temp32=0; diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c index 5fecd3c..d151f3a 100644 --- a/src/southbridge/sis/sis966/sis966.c +++ b/src/southbridge/sis/sis966/sis966.c @@ -33,7 +33,7 @@ #include <device/pci_ops.h> #include "sis966.h"
-static uint32_t final_reg; +static u32 final_reg;
static device_t find_lpc_dev( device_t dev, unsigned devfn) { @@ -47,7 +47,7 @@ static device_t find_lpc_dev( device_t dev, unsigned devfn) if ((lpc_dev->vendor != PCI_VENDOR_ID_SIS) || ( (lpc_dev->device != PCI_DEVICE_ID_SIS_SIS966_LPC) ) ) { - uint32_t id; + u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); if ( (id < (PCI_VENDOR_ID_SIS | (PCI_DEVICE_ID_SIS_SIS966_LPC << 16))) ) { @@ -62,13 +62,13 @@ void sis966_enable(device_t dev) { device_t lpc_dev = 0; device_t sm_dev = 0; - uint16_t index = 0; - uint16_t index2 = 0; - uint32_t reg_old, reg; - uint8_t byte; - uint16_t deviceid; - uint16_t vendorid; - uint16_t devfn; + u16 index = 0; + u16 index2 = 0; + u32 reg_old, reg; + u8 byte; + u16 deviceid; + u16 vendorid; + u16 devfn;
struct southbridge_sis_sis966_config *conf; conf = dev->chip_info; diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c index c33f0fc..1c78441 100644 --- a/src/southbridge/sis/sis966/usb.c +++ b/src/southbridge/sis/sis966/usb.c @@ -30,7 +30,7 @@ #include <device/pci_ops.h> #include "sis966.h"
-uint8_t SiS_SiS7001_init[16][3]={ +u8 SiS_SiS7001_init[16][3]={ {0x04, 0x00, 0x07}, {0x0C, 0x00, 0x08}, {0x0D, 0x00, 0x20}, @@ -59,7 +59,7 @@ static void usb_init(struct device *dev)
//-------------- enable USB1.1 (SiS7001) ------------------------- { - uint8_t temp8; + u8 temp8; int i=0;
while(SiS_SiS7001_init[i][0] != 0) diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 50d50f3..54858bb 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -121,7 +121,7 @@ chrome_vga_init(struct device *dev) static void chrome_init(struct device *dev) { - uint32_t fb_size, fb_address; + u32 fb_size, fb_address;
fb_size = k8m890_host_fb_size_get(); if (!fb_size) { diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 74351bc..2be94a8 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -113,7 +113,7 @@ static void host_ctrl_enable_k8m8xx(struct device *dev) { pci_write_config8(dev, 0xa6, 0x83);
} -void backup_top_of_ram(uint64_t ramtop) { +void backup_top_of_ram(u64 ramtop) { outl((u32) ramtop, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_TOP_OF_RAM); }
diff --git a/src/southbridge/via/vt8235/early_serial.c b/src/southbridge/via/vt8235/early_serial.c index b9bec5f..f511407 100644 --- a/src/southbridge/via/vt8235/early_serial.c +++ b/src/southbridge/via/vt8235/early_serial.c @@ -8,25 +8,25 @@ #define SIO_BASE 0x3f0 #define SIO_DATA SIO_BASE+1
-static void vt8235_writepnpaddr(uint8_t val) +static void vt8235_writepnpaddr(u8 val) { outb(val, 0x2e); outb(val, 0xeb); }
-static void vt8235_writepnpdata(uint8_t val) +static void vt8235_writepnpdata(u8 val) { outb(val, 0x2f); outb(val, 0xeb); }
-static void vt8235_writesiobyte(uint16_t reg, uint8_t val) +static void vt8235_writesiobyte(u16 reg, u8 val) { outb(val, reg); }
-static void vt8235_writesioword(uint16_t reg, uint16_t val) +static void vt8235_writesioword(u16 reg, u16 val) { outw(val, reg); } diff --git a/src/southbridge/via/vt8235/nic.c b/src/southbridge/via/vt8235/nic.c index 71f169c..bba2535 100644 --- a/src/southbridge/via/vt8235/nic.c +++ b/src/southbridge/via/vt8235/nic.c @@ -10,7 +10,7 @@ */ static void nic_init(struct device *dev) { - uint8_t byte; + u8 byte;
printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n");
diff --git a/src/southbridge/via/vt82c686/early_serial.c b/src/southbridge/via/vt82c686/early_serial.c index 55742a7..48168a8 100644 --- a/src/southbridge/via/vt82c686/early_serial.c +++ b/src/southbridge/via/vt82c686/early_serial.c @@ -36,7 +36,7 @@ * @param index The index of the register to modify. * @param value The value to write into the register. */ -static void vt82c686_sio_write(uint8_t index, uint8_t value) +static void vt82c686_sio_write(u8 index, u8 value) { outb(index, SIO_INDEX); outb(value, SIO_DATA); @@ -50,7 +50,7 @@ static void vt82c686_sio_write(uint8_t index, uint8_t value) */ static void vt82c686_enable_serial(device_t dev, unsigned iobase) { - uint8_t reg; + u8 reg; device_t sbdev;
/* TODO: Use info from 'dev' and 'iobase'. */ diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c index 80258a9..ca100f2 100644 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -37,7 +37,7 @@
/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the LDN the register belongs to, before you can access the register. */ -static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) +static void fdc37m60x_sio_write(u8 ldn, u8 index, u8 value) { outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); diff --git a/src/vendorcode/amd/agesa/f10/Lib/amdlib.c b/src/vendorcode/amd/agesa/f10/Lib/amdlib.c index 860fb54..71c53ec 100644 --- a/src/vendorcode/amd/agesa/f10/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f10/Lib/amdlib.c @@ -345,7 +345,7 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - uint8_t bit = 31; + u8 bit = 31; do { if (value & (1 << 31)) return bit; diff --git a/src/vendorcode/amd/agesa/f12/Lib/amdlib.c b/src/vendorcode/amd/agesa/f12/Lib/amdlib.c index 9ce10b6..8b87fed 100644 --- a/src/vendorcode/amd/agesa/f12/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f12/Lib/amdlib.c @@ -349,7 +349,7 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - uint8_t bit = 31; + u8 bit = 31; do { if (value & (1 << 31)) return bit; diff --git a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c index 24c162a..93ea7bf 100644 --- a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c @@ -349,7 +349,7 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - uint8_t bit = 31; + u8 bit = 31; do { if (value & (1 << 31)) return bit; diff --git a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c index 90b0272..6a78309 100644 --- a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c @@ -349,7 +349,7 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - uint8_t bit = 31; + u8 bit = 31; do { if (value & (1 << 31)) return bit; diff --git a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c index 1e2e349..664af8c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f15tn/Lib/amdlib.c @@ -360,7 +360,7 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - uint8_t bit = 31; + u8 bit = 31; do { if (value & (1 << 31)) return bit; diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c index 75354f9..d21d26c 100644 --- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c @@ -361,7 +361,7 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - uint8_t bit = 31; + u8 bit = 31; do { if (value & (1 << 31)) return bit; diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index 26b01ee..0463a3c 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -31,20 +31,20 @@ enum { };
struct vpd_gets_arg { - const uint8_t *key; - const uint8_t *value; - int32_t key_len, value_len; + const u8 *key; + const u8 *value; + s32 key_len, value_len; int matched; };
-static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) +static int cros_vpd_load(u8 **vpd_address, s32 *vpd_size) { STATIC_VAR int cached = 0; - STATIC_VAR uint8_t *cached_address = NULL; - STATIC_VAR int32_t cached_size = 0; + STATIC_VAR u8 *cached_address = NULL; + STATIC_VAR s32 cached_size = 0; STATIC_VAR int result = -1; struct google_vpd_info info; - int32_t base; + s32 base;
const struct fmap_area *area; struct cbfs_media media; @@ -92,8 +92,8 @@ static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) return result; }
-static int vpd_gets_callback(const uint8_t *key, int32_t key_len, - const uint8_t *value, int32_t value_len, +static int vpd_gets_callback(const u8 *key, s32 key_len, + const u8 *value, s32 value_len, void *arg) { struct vpd_gets_arg *result = (struct vpd_gets_arg *)arg; @@ -111,8 +111,8 @@ static int vpd_gets_callback(const uint8_t *key, int32_t key_len,
char *cros_vpd_gets(const char *key, char *buffer, int size) { - uint8_t *vpd_address = NULL; - int32_t vpd_size = 0; + u8 *vpd_address = NULL; + s32 vpd_size = 0; struct vpd_gets_arg arg = {0}; int consumed = 0;
@@ -120,7 +120,7 @@ char *cros_vpd_gets(const char *key, char *buffer, int size) return NULL; }
- arg.key = (const uint8_t *)key; + arg.key = (const u8 *)key; arg.key_len = strlen(key);
while (VPD_OK == decodeVpdString(vpd_size, vpd_address, &consumed, diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 528143c..ac35d65 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -89,7 +89,7 @@ void chromeos_set_me_hash(u32 *hash, int len) memcpy(me_hash_saved, hash, len*sizeof(u32)); }
-void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size) +void acpi_get_vdat_info(u64 *vdat_addr, u32 *vdat_size) { *vdat_addr = (intptr_t)vboot_data; *vdat_size = sizeof(*vboot_data); diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c index a13726d..50f88bb 100644 --- a/src/vendorcode/google/chromeos/vbnv_cmos.c +++ b/src/vendorcode/google/chromeos/vbnv_cmos.c @@ -61,14 +61,14 @@ static inline int is_vbnv_initialized(void) return car_get_var(vbnv_initialized); }
-static inline uint8_t *vbnv_data_addr(int index) +static inline u8 *vbnv_data_addr(int index) { - uint8_t *vbnv_arr = car_get_var_ptr(vbnv); + u8 *vbnv_arr = car_get_var_ptr(vbnv);
return &vbnv_arr[index]; }
-static inline uint8_t vbnv_data(int index) +static inline u8 vbnv_data(int index) { return *vbnv_data_addr(index); } @@ -78,7 +78,7 @@ static inline uint8_t vbnv_data(int index) * worth the code size. */
-static uint8_t crc8(const uint8_t * data, int len) +static u8 crc8(const u8 * data, int len) { unsigned crc = 0; int i, j; @@ -92,10 +92,10 @@ static uint8_t crc8(const uint8_t * data, int len) } }
- return (uint8_t) (crc >> 8); + return (u8) (crc >> 8); }
-void read_vbnv(uint8_t *vbnv_copy) +void read_vbnv(u8 *vbnv_copy) { int i;
@@ -116,7 +116,7 @@ void read_vbnv(uint8_t *vbnv_copy) } }
-void save_vbnv(const uint8_t *vbnv_copy) +void save_vbnv(const u8 *vbnv_copy) { int i;
diff --git a/src/vendorcode/google/chromeos/vbnv_ec.c b/src/vendorcode/google/chromeos/vbnv_ec.c index 78da541..b54d27a 100644 --- a/src/vendorcode/google/chromeos/vbnv_ec.c +++ b/src/vendorcode/google/chromeos/vbnv_ec.c @@ -61,14 +61,14 @@ static inline int is_vbnv_initialized(void) return car_get_var(vbnv_initialized); }
-static inline uint8_t *vbnv_data_addr(int index) +static inline u8 *vbnv_data_addr(int index) { - uint8_t *vbnv_arr = car_get_var_ptr(vbnv); + u8 *vbnv_arr = car_get_var_ptr(vbnv);
return &vbnv_arr[index]; }
-static inline uint8_t vbnv_data(int index) +static inline u8 vbnv_data(int index) { return *vbnv_data_addr(index); } @@ -78,7 +78,7 @@ static inline uint8_t vbnv_data(int index) * worth the code size. */
-static uint8_t crc8(const uint8_t * data, int len) +static u8 crc8(const u8 * data, int len) { unsigned crc = 0; int i, j; @@ -92,10 +92,10 @@ static uint8_t crc8(const uint8_t * data, int len) } }
- return (uint8_t) (crc >> 8); + return (u8) (crc >> 8); }
-void read_vbnv(uint8_t *vbnv_copy) +void read_vbnv(u8 *vbnv_copy) { google_chromeec_vbnv_context(1, vbnv_copy, VBNV_BLOCK_SIZE);
@@ -113,9 +113,9 @@ void read_vbnv(uint8_t *vbnv_copy) } }
-void save_vbnv(const uint8_t *vbnv_copy) +void save_vbnv(const u8 *vbnv_copy) { - google_chromeec_vbnv_context(0, (uint8_t *)vbnv_copy, VBNV_BLOCK_SIZE); + google_chromeec_vbnv_context(0, (u8 *)vbnv_copy, VBNV_BLOCK_SIZE); }
static void vbnv_setup(void) diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c index 7ef2c7e..7271db6 100644 --- a/src/vendorcode/google/chromeos/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot_handoff.c @@ -153,7 +153,7 @@ const struct payload_loader_ops vboot_payload_loader = { .locate = vboot_locate_payload, };
-int vboot_get_handoff_info(void **addr, uint32_t *size) +int vboot_get_handoff_info(void **addr, u32 *size) { struct vboot_handoff *vboot_handoff;
diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 80e2aea..68afdab 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -44,12 +44,12 @@ * signed firmware region based off of the embedded metadata. */
struct component_entry { - uint32_t offset; - uint32_t size; + u32 offset; + u32 size; } __attribute__((packed));
struct components { - uint32_t num_components; + u32 num_components; struct component_entry entries[0]; } __attribute__((packed));
@@ -101,7 +101,7 @@ static void locate_region(const char *name, struct vboot_region *region) static int fw_region_size(struct vboot_region *r) { struct components *fw_info; - int32_t size; + s32 size; size_t req_size; int i;
@@ -121,7 +121,7 @@ static int fw_region_size(struct vboot_region *r) size += sizeof(struct component_entry) * fw_info->num_components;
for (i = 0; i < fw_info->num_components; i++) - size += ALIGN(fw_info->entries[i].size, sizeof(uint32_t)); + size += ALIGN(fw_info->entries[i].size, sizeof(u32));
/* Check that size of comopnents does not exceed the region's size. */ if (size > r->size) @@ -234,7 +234,7 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) VbCommonParams cparams; VbSelectFirmwareParams fparams; struct vboot_context context; - uint32_t *iflags; + u32 *iflags;
vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY;
@@ -307,7 +307,7 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) }
#if CONFIG_RELOCATABLE_RAMSTAGE -static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, +static void *vboot_load_ramstage(u32 cbmem_id, const char *name, const struct cbmem_entry **cbmem_entry) { struct vboot_handoff *vboot_handoff; diff --git a/src/vendorcode/google/chromeos/vboot_wrapper.c b/src/vendorcode/google/chromeos/vboot_wrapper.c index 5aa0066..f83e9fb 100644 --- a/src/vendorcode/google/chromeos/vboot_wrapper.c +++ b/src/vendorcode/google/chromeos/vboot_wrapper.c @@ -74,7 +74,7 @@ void VbExDebug(const char *format, ...) va_end(args); }
-uint64_t VbExGetTimer(void) +u64 VbExGetTimer(void) { #if CONFIG_ARCH_X86 return rdtscll(); @@ -85,13 +85,13 @@ uint64_t VbExGetTimer(void) #endif }
-VbError_t VbExNvStorageRead(uint8_t *buf) +VbError_t VbExNvStorageRead(u8 *buf) { gcontext->read_vbnv(buf); return VBERROR_SUCCESS; }
-VbError_t VbExNvStorageWrite(const uint8_t *buf) +VbError_t VbExNvStorageWrite(const u8 *buf) { gcontext->save_vbnv(buf); return VBERROR_SUCCESS; @@ -134,20 +134,20 @@ void VbExFree(void *ptr) /* vboot doesn't expose these through the vboot_api.h, but they are needed. * coreboot requires declarations so provide them to avoid compiler errors. */ int Memcmp(const void *src1, const void *src2, size_t n); -void *Memcpy(void *dest, const void *src, uint64_t n); -void *Memset(void *dest, const uint8_t c, uint64_t n); +void *Memcpy(void *dest, const void *src, u64 n); +void *Memset(void *dest, const u8 c, u64 n);
int Memcmp(const void *src1, const void *src2, size_t n) { return memcmp(src1, src2, n); }
-void *Memcpy(void *dest, const void *src, uint64_t n) +void *Memcpy(void *dest, const void *src, u64 n) { return memcpy(dest, src, n); }
-void *Memset(void *dest, const uint8_t c, uint64_t n) +void *Memset(void *dest, const u8 c, u64 n) { return memset(dest, c, n); } @@ -162,9 +162,9 @@ static inline size_t get_hash_block_size(size_t requested_size) return requested_size; }
-VbError_t VbExHashFirmwareBody(VbCommonParams *cparams, uint32_t firmware_index) +VbError_t VbExHashFirmwareBody(VbCommonParams *cparams, u32 firmware_index) { - uint8_t *data; + u8 *data; struct vboot_region *region; struct vboot_context *ctx; size_t data_size; @@ -222,8 +222,8 @@ VbError_t VbExTpmOpen(void) return VBERROR_SUCCESS; }
-VbError_t VbExTpmSendReceive(const uint8_t *request, uint32_t request_length, - uint8_t *response, uint32_t *response_length) +VbError_t VbExTpmSendReceive(const u8 *request, u32 request_length, + u8 *response, u32 *response_length) { size_t len = *response_length; if (gcontext->tis_sendrecv(request, request_length, response, &len)) @@ -237,8 +237,8 @@ VbError_t VbExTpmSendReceive(const uint8_t *request, uint32_t request_length,
#if !CONFIG_SPI_FLASH_MEMORY_MAPPED VbError_t VbExRegionRead(VbCommonParams *cparams, - enum vb_firmware_region region, uint32_t offset, - uint32_t size, void *buf) + enum vb_firmware_region region, u32 offset, + u32 size, void *buf) { struct vboot_context *ctx; VbExDebug("VbExRegionRead: offset=%x size=%x, buf=%p\n", diff --git a/src/vendorcode/google/chromeos/vpd_decode.c b/src/vendorcode/google/chromeos/vpd_decode.c index 545fd81..92fc209 100644 --- a/src/vendorcode/google/chromeos/vpd_decode.c +++ b/src/vendorcode/google/chromeos/vpd_decode.c @@ -8,11 +8,11 @@ #include "lib_vpd.h"
int decodeLen( - const int32_t max_len, - const uint8_t *in, - int32_t *length, - int32_t *decoded_len) { - uint8_t more; + const s32 max_len, + const u8 *in, + s32 *length, + s32 *decoded_len) { + u8 more; int i = 0;
assert(length); @@ -35,15 +35,15 @@ int decodeLen( /* Sequentially decodes type, key, and value. */ int decodeVpdString( - const int32_t max_len, - const uint8_t *input_buf, - int32_t *consumed, + const s32 max_len, + const u8 *input_buf, + s32 *consumed, VpdDecodeCallback callback, void *callback_arg) { int type; - int32_t key_len, value_len; - int32_t decoded_len; - const uint8_t *key, *value; + s32 key_len, value_len; + s32 decoded_len; + const u8 *key, *value;
/* type */ if (*consumed >= max_len) diff --git a/src/vendorcode/intel/fsp/baytrail/srx/board_fsp.c b/src/vendorcode/intel/fsp/baytrail/srx/board_fsp.c index 2cb3492..1d2d41f 100644 --- a/src/vendorcode/intel/fsp/baytrail/srx/board_fsp.c +++ b/src/vendorcode/intel/fsp/baytrail/srx/board_fsp.c @@ -38,8 +38,7 @@ are permitted provided that the following conditions are met: #include "fsp.h"
void -GetLowMemorySize ( - uint32_t *LowMemoryLength +GetLowMemorySize (u32 *LowMemoryLength ) { EFI_PEI_HOB_POINTERS Hob; @@ -62,7 +61,7 @@ GetLowMemorySize ( // if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 && Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) { - *LowMemoryLength += (uint32_t) (Hob.ResourceDescriptor->ResourceLength); + *LowMemoryLength += (u32) (Hob.ResourceDescriptor->ResourceLength); } } } @@ -73,8 +72,7 @@ GetLowMemorySize ( }
void -GetHighMemorySize ( - uint64_t *HighMemoryLength +GetHighMemorySize (u64 *HighMemoryLength ) { EFI_PEI_HOB_POINTERS Hob; @@ -96,7 +94,7 @@ GetHighMemorySize ( // Need memory above 4GB to be collected here // if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) { - *HighMemoryLength += (uint64_t) (Hob.ResourceDescriptor->ResourceLength); + *HighMemoryLength += (u64) (Hob.ResourceDescriptor->ResourceLength); } } } @@ -107,9 +105,8 @@ GetHighMemorySize ( }
void -GetFspReservedMemoryFromGuid ( - uint32_t *FspMemoryBase, - uint32_t *FspMemoryLength, +GetFspReservedMemoryFromGuid (u32 *FspMemoryBase, + u32 *FspMemoryLength, EFI_GUID FspReservedMemoryGuid ) { @@ -129,8 +126,8 @@ GetFspReservedMemoryFromGuid ( if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) { if (CompareGuid(&Hob.ResourceDescriptor->Owner, &FspReservedMemoryGuid)) { - *FspMemoryBase = (uint32_t) (Hob.ResourceDescriptor->PhysicalStart); - *FspMemoryLength = (uint32_t) (Hob.ResourceDescriptor->ResourceLength); + *FspMemoryBase = (u32) (Hob.ResourceDescriptor->PhysicalStart); + *FspMemoryLength = (u32) (Hob.ResourceDescriptor->ResourceLength); break; } } @@ -144,12 +141,12 @@ GetFspReservedMemoryFromGuid ( void GetFspNVStorageMemory ( VOID **FspNVStorageHob, - uint16_t *DataSize + u16 *DataSize ) {
EFI_GUID FspNVStorageHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - uint8_t *GuidHob; + u8 *GuidHob; EFI_HOB_GENERIC_HEADER *GuidHobHdr;
GuidHob = GetFirstGuidHob(&FspNVStorageHobGuid); @@ -166,12 +163,12 @@ GetFspNVStorageMemory ( void GetTempRamStack ( VOID **TempRamStackPtr, - uint16_t *DataSize + u16 *DataSize ) {
EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; - uint8_t *GuidHob; + u8 *GuidHob; EFI_HOB_GENERIC_HEADER *GuidHobHdr;
GuidHob = GetFirstGuidHob(&FspBootloaderTemporaryMemoryHobGuid);