Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81040?usp=email )
(
27 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Redefine data types for GNR ......................................................................
soc/intel/xeon_sp: Redefine data types for GNR
Granite Rapids (6th Gen Xeon-SP) FSP introduces UDS_STACK_RES/ UDS_SOCKET_RES and retires the usages of STACK_RES/ IIO_RESOURCE_INSTANCE. Make redinitions to make Xeon-SP common codes to work for both 6th Gen before and later.
Change-Id: I28c948525cd6d7ac4b9c3fa67e3c99ec637ed38f Signed-off-by: Shuo Liu shuo.liu@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/81040 Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h 6 files changed, 23 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 66f7169..1ddfe8b 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -211,7 +211,7 @@ if (!soc_cpu_is_enabled(s)) continue; for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + const xSTACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; const size_t seg = hob->PlatformData.CpuQpiInfo[s].PcieSegment;
if (ri->BusBase > ri->BusLimit) diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index d1ce7bf..60b2a82 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -6,6 +6,9 @@ #include <hob_iiouds.h> #include <hob_memmap.h>
+#define xSTACK_RES STACK_RES +#define xIIO_RESOURCE_INSTANCE IIO_RESOURCE_INSTANCE + /* * Address of the MRC status byte in CMOS. Should be reserved * in mainboards' cmos.layout and not covered by checksum. @@ -22,6 +25,13 @@ #endif #endif
+struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; +}; + +void get_iiostack_info(struct iiostack_resource *info); + const struct SystemMemoryMapHob *get_system_memory_map(void);
uint8_t socket0_get_ubox_busno(const uint8_t stack); diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index ce8e759..3740426 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -53,11 +53,11 @@
void create_ioat_domains(union xeon_domain_path path, struct bus *bus, - const STACK_RES *sr, + const xSTACK_RES *sr, const size_t pci_segment_group);
void create_xeonsp_domains(const union xeon_domain_path dp, struct bus *bus, - const STACK_RES *sr, const size_t pci_segment_group); + const xSTACK_RES *sr, const size_t pci_segment_group);
void create_domain(const union xeon_domain_path dp, struct bus *upstream, int bus_base, int bus_limit, const char *type, diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index eff8c08..5904b16 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -23,16 +23,10 @@ bool is_memtype_reserved(uint16_t mem_type); bool is_memtype_processor_attached(uint16_t mem_type);
-struct iiostack_resource { - uint8_t no_of_stacks; - STACK_RES res[CONFIG_MAX_SOCKET * MAX_IIO_STACK]; -}; - -void get_iiostack_info(struct iiostack_resource *info); -bool is_pcie_iio_stack_res(const STACK_RES *res); -bool is_ubox_stack_res(const STACK_RES *res); -bool is_ioat_iio_stack_res(const STACK_RES *res); -bool is_iio_cxl_stack_res(const STACK_RES *res); +bool is_pcie_iio_stack_res(const xSTACK_RES *res); +bool is_ubox_stack_res(const xSTACK_RES *res); +bool is_ioat_iio_stack_res(const xSTACK_RES *res); +bool is_iio_cxl_stack_res(const xSTACK_RES *res); void bios_done_msr(void *unused);
#endif diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 0c4f998..b8c000e 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -6,6 +6,9 @@ #include <hob_iiouds.h> #include <hob_memmap.h>
+#define xSTACK_RES STACK_RES +#define xIIO_RESOURCE_INSTANCE IIO_RESOURCE_INSTANCE + void config_reset_cpl3_csrs(void);
const struct SystemMemoryMapHob *get_system_memory_map(void); diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h index bf81f3d..463e619 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h @@ -9,6 +9,9 @@ #include <hob_systeminfo.h> #include <hob_enhancedwarningloglib.h>
+#define xSTACK_RES STACK_RES +#define xIIO_RESOURCE_INSTANCE IIO_RESOURCE_INSTANCE + /* * Address of the MRC status byte in CMOS. Should be reserved * in mainboards' cmos.layout and not covered by checksum.