[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42790 )

Change subject: soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry
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Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/42790/2/src/soc/intel/common/block/... 
File src/soc/intel/common/block/cse/cse_lite.c:

https://review.coreboot.org/c/coreboot/+/42790/2/src/soc/intel/common/block/... 
PS2, Line 364: BS_DEV_INIT_CHIPS
> This will affect CML/JSL platforms. Without evaluating , we cann't have this change.

Ack

https://review.coreboot.org/c/coreboot/+/42790/5/src/soc/intel/common/block/... 
File src/soc/intel/common/block/cse/cse_lite.c:

https://review.coreboot.org/c/coreboot/+/42790/5/src/soc/intel/common/block/... 
PS5, Line 364: #if CONFIG(SOC_INTEL_TIGERLAKE)
             : BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL);
             : #else
> I added a note to the bug that this CL needs to be reverted as part of the bug closing process.

Ack