Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41563 )
Change subject: Documentation: Add section about 'hidden' devices to 4.13 release notes ......................................................................
Documentation: Add section about 'hidden' devices to 4.13 release notes
CB:41384 added some new functionality to devicetree files ("hidden PCI devices"). It's a decent enough semantic change that it should be added to the release notes for the 4.13 release.
Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M Documentation/releases/coreboot-4.13-relnotes.md 1 file changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/41563/1
diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 94e93bb..0175250 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -13,4 +13,17 @@ Significant changes -------------------
-### Add significant changes here +### Hidden PCI devices + +This new functionality takes advantage of the existing 'hidden' keyword in the +devicetree. Since no existing boards were using the keyword, its usage was +repurposed to make dealing with some unique PCI devices easier. The particular +case here is Intel's PMC (Power Management Controller). During the FSP-S run, +the PMC device is made hidden, meaning that its config space looks as if there +is no device there (Vendor ID reads as 0xFFFF_FFFF). However, the device does +have fixed resources, both MMIO and I/O. These were previously recorded in +different places (MMIO was typically an SA fixed resource, and I/O was treated +as an LPC resource). With this change, when a device in the tree is marked as +'hidden', it is not probed (`pci_probe_dev()`) but rather assumed to exist so +that its resources can be placed in a more natural location. This also adds the +ability for the device to participate in SSDT generation.